Run-time integration of reconfigurable video processing systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 9, 2007, Pages 1003-1016

  Sedecole, Pete ^a,b   Cheung, Peter Y K ^a,b   Constantinides, George A ^a,b   Luk, Wayne ^a,b  

^a IEEE

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Adaptive systems; Bus architecture; Design automation; Field programmable gate arrays (fpgas); On chip communication; Platform based design; Reconfigurable architectures; Video processing

Indexed keywords

ADAPTIVE SYSTEMS; COMMUNICATION CHANNELS (INFORMATION THEORY); EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

BUS ARCHITECTURE; DESIGN AUTOMATION; ON-CHIP COMMUNICATION; PLATFORM-BASED DESIGN; RECONFIGURABLE ARCHITECTURES;

IMAGE PROCESSING;

EID: 34548072006     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.902203     Document Type: Article

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