SCOPUS 정보 검색 플랫폼

Volumn 11, Issue 10, 2014, Pages

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme

(8) Matsunaga, Shoun a Mochizuki, Akira a Sakimura, Noboru b Nebashi, Ryusuke b Sugibayashi, Tadahiko b Endoh, Tetsuo a Ohno, Hideo a Hanyu, Takahiro a

a TOHOKU UNIVERSITY (Japan)

b NEC CORPORATION (Japan)

Author keywords

Associative memory; Bit parallel; Complementary; Process variation; Spintronics; STT

Indexed keywords

ASSOCIATIVE PROCESSING; ASSOCIATIVE STORAGE; CELLS; CYTOLOGY; LOGIC GATES; MEMORY ARCHITECTURE; SPINTRONICS; TERNARY CONTENT ADRESSABLE MEMORY; TIMING CIRCUITS; TUNNEL JUNCTIONS;

ASSOCIATIVE MEMORY; BIT-PARALLEL; CELL STRUCTURE; COMPLEMENTARY; MAGNETIC TUNNEL JUNCTION; OUTPUT VOLTAGE SWINGS; PROCESS VARIATION; TERNARY CONTENT ADDRESSABLE MEMORY;

MAGNETIC DEVICES;

EID: 84901450602 PISSN: 13492543 EISSN: None Source Type: Journal
DOI: 10.1587/elex.11.20140297 Document Type: Article

Times cited : (9)

References (7)

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- DOI:10.1063/1.3677875
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- DOI:10.7567/JJAP.51.02BM06
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7
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.