Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 298-299

  Matsunaga, Shoun ^a   Katsumata, Akira ^a   Natsui, Masanori ^a   Fukami, Shunsuke ^a   Endoh, Tetsuo ^a   Ohno, Hideo ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-PARALLEL; CELL CIRCUITS; CONTROL MECHANISM; DISCHARGE CONTROL; LEAKAGE POWER; MATCH LINE; NMOS TRANSISTORS; NON-VOLATILE;

VLSI CIRCUITS;

EID: 80052671472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. S. Matsunaga, et al., APEX, vol.2, no.2, p.023004, Feb. 2009.
3. S. Matsunaga, et. al., JJAP, vol.49, no.4, p.04DM05, Apr. 2010.
4. I. Arsovski, et al., JSSC, vol.38, no.1, pp.155-158, Jan. 2003.
5. K. Pagiamtzis, et al., JSSC, vol.41, no.3, pp.712-727, Mar. 2006.