A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 44-45

  Matsunaga, Shoun ^a   Miura, Sadahiko ^b   Honjou, Hiroaki ^b   Kinoshita, Keizo ^a   Ikeda, Shoji ^a   Endoh, Tetsuo ^a   Ohno, Hideo ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; CELL CIRCUITS; CELL SIZE; LOGIC FUNCTIONS; LOGIC-IN-MEMORY ARCHITECTURE; NON-VOLATILE; TRANSISTOR COUNT;

CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; LOGIC GATES; MEMORY ARCHITECTURE; STATIC RANDOM ACCESS STORAGE; TERNARY CONTENT ADRESSABLE MEMORY; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 84866613380     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243781     Document Type: Conference Paper

References (8)

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