60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 42-43

  Chiang, Ping Chuan ^a,b   Hung, Hao Wei ^a   Chu, Hsiang Yun ^a   Chen, Guan Sing ^a   Lee, Jri ^a,b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b Atilia Technology   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; TRANSCEIVERS;

65NM CMOS; CMOS TECHNOLOGY; DATA RATES; FULLY INTEGRATED; OPERATING SPEED; PAM4 TRANSMITTERS; RECENT RESEARCHES; TELECOM SYSTEMS;

ETHERNET;

EID: 84898069455     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757329     Document Type: Conference Paper

References (8)

1. J. Jiang et al., "100Gb/s Ethernet Chipsets in 65nm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 120-121, Feb. 2013.
2. S. Zhai et al., "The Requirement Analysis of 400GE FEC for Gen1 PMDs," IEEE 400Gb/s Ethernet Study Group, July 2013. [Online]. Available: http://www.ieee802.org/3/400GSG/public/13-07/zhai-400-01-0713.pdf
3. 40 Gb/s and 100 Gb/s Ethernet Task Force. [Online]. Available: http://www.ieee802.org/3/ba/index.html
4. Jri Lee et al., "A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique," IEEE J. Solid-State Circuits, vol. 43, pp. 1414-1426, Jun. 2008.
5. Jri Lee et al., "Study of Subharmonically Injection-Locked PLLs," IEEE J. Solid-State Circuits, vol. 44, pp. 1539-1553, May 2009.
6. D. Yamazaki et al., "A 25GHz Clock Buffer and a 50Gb/s 2:1 Selector in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 240-241, Feb. 2004.
7. K. Kanda et al., "A Single-40Gb/s Dual-20Gb/s Serializer IC with SFI-5.2 Interface in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 360-361, Feb. 2009.
8. C. Menolfi et al., "A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI," ISSCC Dig. Tech. Papers, pp. 72-73, Feb. 2005.