A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 360-362

  Kanda, Kouichi ^a   Tamura, Hirotaka ^a   Yamamoto, Takuji ^a   Matsubara, Satoshi ^a   Kibune, Masaya ^a   Doi, Yoshiyasu ^a   Shibasaki, Takayuki ^a   Tzartzanis, Nestoras ^b   Kristensson, Anders ^b   Parikh, Samir ^b   Ide, Satoshi ^a   Tsunoda, Yukito ^a   Yamabana, Tetsuji ^a   Sugawara, Mariko ^a   Kuwata, Naoki ^a   Ikeuchi, Tadashi ^a   Ogawa, Junji ^a   Walker, Bill ^b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349268236     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977457     Document Type: Conference Paper

References (5)

1. T. Hoshida, T. Takahara, Y. Akiyama, et al., "Design Optimization of 40 Gb/s RZDQPSK Transceiver for High OSNR and PMD Tolerance under Fast Polarization Changes, " European Conference on Optical Communication, Paper P64, Sept., 2007.
2. J. Kim, J.-K. Kim, B.-J. Lee, et al., "Circuit Techniques for a 40Gb/s Transmitter in 0.13μm CMOS, " ISSCC Dig. Tech. Papers, pp. 150-151, Feb., 2005.
3. J.-K. Kim, J. Kim, G. Kim, et al., "A 40-Gb/s Transceiver in 0.13-μm CMOS Technology, " IEEE Symp. VLSI Circuits, pp. 196-197, Jun., 2008.
4. S. Galal and B. Razavi, "40Gb/s Amplifier and ESD Protection Circuit in 0.18μm CMOS Technology, " ISSCC Dig. Tech. Paper, pp. 480-481, Feb., 2004.
5. C.-F. Liao and S.-L. Liu, "A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS, " ISSCC Dig. Tech. Papers, pp. 54-55, Feb., 2007.