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Volumn 56, Issue , 2013, Pages 120-121

100Gb/s ethernet chipsets in 65nm CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; DATA SEQUENCES; DESERIALIZERS; ELECTRICAL DOMAINS; OPTICAL FRONT-ENDS; OPTICAL SIGNALS; SERIALIZERS; SYSTEM LEVEL INTEGRATION;

EID: 84876526628     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487663     Document Type: Conference Paper
Times cited : (65)

References (8)
  • 1
    • 70449372266 scopus 로고    scopus 로고
    • A 21-gb/s 87-mw transceiver with ffe/dfe/linear equalizer in 65-nm cmos technology
    • June
    • H. Wang, C. Lee, A. Lee, and Jri Lee,"A 21-Gb/s 87-mW Transceiver with FFE/DFE/Linear Equalizer in 65-nm CMOS Technology," IEEE Symp. VLSI Circuits, pp. 50-51, June 2009.
    • (2009) IEEE Symp. VLSI Circuits , pp. 50-51
    • Wang, H.1    Lee, C.2    Lee, A.3    Lee, J.4
  • 2
    • 77952136534 scopus 로고    scopus 로고
    • A 2×25gb/s deserializer with 2:5 dmux for 100gb/s ethernet applications
    • Feb.
    • K. Wu and Jri Lee, "A 2×25Gb/s Deserializer with 2:5 DMUX for 100Gb/s Ethernet Applications," ISSCC Dig. Tech. Papers, pp. 374-375, Feb. 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 374-375
    • Wu, K.1    Lee, J.2
  • 3
    • 70349285140 scopus 로고    scopus 로고
    • A 20gb/s full-rate linear cdr circuit with automatic frequency acquisition
    • Feb.
    • Jri Lee and K. Wu, "A 20Gb/s Full-Rate Linear CDR Circuit with Automatic Frequency Acquisition," ISSCC Dig. Tech. Papers, pp. 366-367, Feb. 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 366-367
    • Lee, J.1    Wu, K.2
  • 4
    • 70349266731 scopus 로고    scopus 로고
    • Subharmonically injection-locked plls for ultra-low- noise clock generation
    • Feb.
    • Jri Lee, H. Wang, W. Chen, and Y. Lee, "Subharmonically Injection-Locked PLLs for Ultra-Low- Noise Clock Generation," ISSCC Dig. Tech. Papers, pp. 92-93, Feb. 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 92-93
    • Lee, J.1    Wang, H.2    Chen, W.3    Lee, Y.4
  • 5
    • 34548827121 scopus 로고    scopus 로고
    • A 20-gb/s adaptive equalizer in 0.13-μm cmos technology
    • Feb.
    • Jri Lee, "A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 92-93, Feb. 2006.
    • (2006) ISSCC Dig. Tech. Papers , pp. 92-93
    • Lee, J.1
  • 6
    • 84860660403 scopus 로고    scopus 로고
    • 25Gb/s 3.6pj/b and 15gb/s 1.37pj/b vcsel-based optical links in 90nm cmos
    • Feb.
    • J. Proesel et al., "25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-Based Optical Links in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 418-420, Feb. 2012.
    • (2012) ISSCC Dig. Tech. Papers , pp. 418-420
    • Proesel, J.1
  • 7
    • 84866617884 scopus 로고    scopus 로고
    • A 25-gb/s 2.2-w optical transceiver using an analog fe tolerant to power supply noise and redundant data format conversion in 65-nm cmos
    • June
    • T. Takemoto et al., "A 25-Gb/s 2.2-W Optical Transceiver Using an Analog FE Tolerant to Power Supply Noise and Redundant Data Format Conversion in 65-nm CMOS," IEEE Symp. VLSI Circuits, pp. 106-107, June 2012.
    • (2012) IEEE Symp. VLSI Circuits , pp. 106-107
    • Takemoto, T.1
  • 8
    • 79955720542 scopus 로고    scopus 로고
    • A 10:4 mux and 4:10 demux gearbox lsi for 100-gigabit ethernet link
    • Feb.
    • G. Ono et al., "A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link," ISSCC Dig. Tech. Papers, pp. 148-150, Feb. 2011.
    • (2011) ISSCC Dig. Tech. Papers , pp. 148-150
    • Ono, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.