A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Yamazaki, Daisuke ^a   Yamamoto, Takuji ^a   Horinaka, Minoru ^a   Nomura, Hiroshi ^a   Hashimoto, Kouichi ^a   Onodera, Hiroyuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK BUFFERS; CLOCK FREQUENCY; LOGIC SUPPLY VOLTAGE;

BANDWIDTH; COMPUTER SIMULATION; ELECTRIC INDUCTORS; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 2442716240     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. M. Green et.al., "OC-192 Transmitter in Standard 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 248-249, Feb. 2002.
2. J. Cao et.al., "OC-192 Receiver in Standard 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 250-251, Feb. 2002.
3. D. Kehrer et.al., "40Gb/s 2:1 Multiplexer and 1:2 Demultiplexer in 120nm CMOS," ISSCC Dig. Tech. Papers, pp. 344-345, Feb. 2003.