A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 244-245

  Frustaci, Fabio ^a,b   Khayatzadeh, Mahmood ^b   Blaauw, David ^b   Sylvester, Dennis ^b   Alioto, Massimo ^c  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF MICHIGAN   (United States)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE REUSABILITY; ENERGY EFFICIENCY; QUALITY MANAGEMENT;

ADVANCED TECHNOLOGY; AGGRESSIVE VOLTAGE SCALING; APPLICATION QUALITY; ENERGY BENEFITS; ENERGY REDUCTION; ERROR FREE OPERATIONS; QUALITY TARGETS; VOLTAGE-SCALING;

MICROPROCESSOR CHIPS;

EID: 84898066852     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757419     Document Type: Conference Paper

References (6)

1. MIN Applications," ISSCC Dig. Tech. Papers, pp. 316-317, 2013.
2. H. Pilo, et al., "A 64Mb SRAM in 22nm SOI Technology Featuring Fine-Granularity Power Gating and Low-Energy Power-Supply-Partition Techniques for 37% Leakage Reduction" ISSCC Dig. Tech. Papers, pp. 322-323, 2013.
3. M. Yabuuchi, et al., "A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations," ISSCC Dig. Tech. Papers, pp. 326-327, 2007.
4. I. J. Chang, et al, "A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications," IEEE TCSVT, vol. 21, no. 2, pp. 101-112, 2011.
5. M.E. Sinangil, A. Chandrakasan, "An SRAM Using Output Prediction to Reduce BL-Switching Activity and Statistically-Gated SA for up to 1.9× Reduction in Energy/Access," ISSCC Dig. Tech. Papers, pp. 318-319, 2013.
6. H. Kaul, et al., "A 1.45GHz 52-to-162GFLOPS/W Variable-Precision Floating-Point Fused Multiply-Add Unit with Certainty Tracking in 32nm CMOS," ISSCC Dig. Tech. Papers, pp. 182-183, 2013.