A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 182-183

  Kaul, Himanshu ^a   Anders, Mark ^a   Mathew, Sanu ^a   Hsu, Steven ^a   Agarwal, Amit ^a   Sheikh, Farhana ^a   Krishnamurthy, Ram ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D GRAPHICS; BUILDING BLOCKES; CLOCK GATING; DATA PATHS; FLOATING POINT UNITS; FLOATING-POINT COMPUTATION; FUSED MULTIPLY-ADD; HIGH-PERFORMANCE COMPUTING; HIGH-PRECISION; HIGH-THROUGHPUT; INCREMENTER; LOWER PRECISION; POWER REDUCTIONS; RECONFIGURABILITY; RUNTIMES; SCALABLE PERFORMANCE; SINGLE CYCLE; ULTRALOW VOLTAGE;

CLOCKS; COMPUTER SOFTWARE SELECTION AND EVALUATION; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; SIGNAL PROCESSING;

DIGITAL ARITHMETIC;

EID: 84860691732     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176987     Document Type: Conference Paper

References (4)

1. H.-J. Oh, et al., "A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL Processor", IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 759-771, 2006.
2. B. Curran, et al., "4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6 Processor", ISSCC Dig. Tech. Papers, pp. 436-437, 2006.
3. M. J. Schulte, et al., "A Family of Variable-Precision Interval Arithmetic Processors," IEEE Trans. on Computers, vol. 49, no. 5, pp. 387-397, May 2000.
4. nd generation highk/metal gate transistors optimized for ultra low power, high performance, and high density product applications", IEEE IEDM Dig. Tech. Papers, pp. 1-4, 2009.