A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 338-339

  Fackenthal, Richard ^a   Kitagawa, Makoto ^b   Otsuka, Wataru ^b   Prall, Kirk ^a   Mills, Duane ^a   Tsutsui, Keiichi ^b   Javanifard, Jahanshir ^a   Tedrow, Kerry ^a   Tsushima, Tomohito ^b   Shibahara, Yoshiyuki ^b   Hush, Glen ^a  

^a MICRON TECHNOLOGY INC   (United States)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY;

DATA-PATH ARCHITECTURE; HIGH-DENSITY ARRAYS; HIGH-DENSITY DEVICES; LOW DENSITY; LOW POWER; RESISTIVE RAMS;

NANOTECHNOLOGY;

EID: 84898064465     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757460     Document Type: Conference Paper

References (5)

1. 2 2-Layer 32Gb ReRAM Memory Device in 24nm Technology", ISSCC Dig. Tech. Papers, pp. 210-211, Feb. 2013.
2. A. Kawahara, R. Azuma, et al., "An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput", ISSCC Dig. Tech. Papers, pp. 432-433, Feb. 2012.
3. W. Otsuka, K. Miyata, et al., "A 4Mb Conductive-Bridge Resistive Memory with 2.3GB/s Read-Throughput and 216MB/s Program-Throughput", ISSCC Dig. Tech. Papers, pp. 210-211, Feb., 2011.
4. J. Yi, H. Choi, et al., "Highly Reliable and Fast Nonvolatile Hybrid Switching ReRAM Memory Using Thin Al2O3 Demonstrated at 54nm memory Array", Symposium on VLSI Technology (VLSIT), pp. 48-49, 2011
5. yO resistive memory with self-adaptive yield enhancement and operation power reduction", Symposium on VLSI Technology (VLSIT), pp. 42-43, 2012.