Impact of stress mode on stochastic BTI in scaled MG/HK CMOS devices

IEEE Electron Device Letters

Volumn 35, Issue 4, 2014, Pages 431-433

  Kerber, Andreas ^a   Srinivasan, Purushothaman ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Bias temperature instability; CMOS devices; high k dielectrics; metal gate; variability

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS; STOCHASTIC SYSTEMS;

BIAS TEMPERATURE INSTABILITY; CMOS DEVICES; HIGH-K DIELECTRIC; METAL GATE; VARIABILITY;

INTEGRATED CIRCUITS;

EID: 84897913730     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2014.2304532     Document Type: Article

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