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Volumn , Issue , 2012, Pages 129-130
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High performance bulk planar 20nm CMOS technology for low power mobile applications
a a a a a a a a a a a a a a a a a a a a more.. |
Author keywords
[No Author keywords available]
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Indexed keywords
BULK TECHNOLOGIES;
CMOS TECHNOLOGY;
CO-OPTIMIZATION;
COMPUTING APPLICATIONS;
DENSITY SCALING;
DRIVE CURRENTS;
HIGH DENSITY WIRING;
LOW POWER;
LOW POWER TECHNOLOGIES;
METAL GATE;
MOBILE APPLICATIONS;
STANDBY POWER;
STATIC NOISE MARGIN;
STRAIN ENGINEERING;
CMOS INTEGRATED CIRCUITS;
DIELECTRIC MATERIALS;
GATE DIELECTRICS;
TECHNOLOGY;
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EID: 84866526221
PISSN: 07431562
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/VLSIT.2012.6242495 Document Type: Conference Paper |
Times cited : (31)
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References (7)
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