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3
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84893731044
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More information and related papers are available at the memory management related http: web site of VSDM
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More information and related papers are available at the memory management related http: web site of VSDM: //www.imec.be/vsdm/projects/atomium/ index.html.
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4
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0030193484
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Image processing on high-performance risc systems
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July
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P.Balietto, M.Maresca, M.Migliardi, N.Zingirian, "Image processing on high-performance RISC systems", Proc. of the IEEE, invited paper, Vol.84, No.7, pp.917-930, July 1996.
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Proc. of the IEEE, Invited Paper
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Balietto, P.1
Maresca, M.2
Migliardi, M.3
Zingirian, N.4
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5
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0031070116
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A 350 mhz 3.3v 4mb sram fabricated in a 0.3 μm cmos process
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Feb.
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G.Braceras, D.Evans, J.Sousa, J.Connor, "A 350 MHz 3.3V 4Mb SRAM fabricated in a 0.3 μm CMOS process", Proc. IEEE Int. Solid-State Circ. Conf., San Francisco CA, pp.404-405, Feb. 1997.
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Proc. IEEE Int. Solid-State Circ. Conf., San Francisco CA
, pp. 404-405
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Braceras, G.1
Evans, D.2
Sousa, J.3
Connor, J.4
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7
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0028754935
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Global communication and memory optimizing transformations for low power signal processing systems
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La Jolla CA, Oct. 1994. Also in VLSI Signal Processing VII, J.Rabaey, P.Chau, J.Eldon (eds.), IEEE Press, New York
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F.Catthoor, F.Franssen, S.Wuytack, L.Nachtergaele, H.De Man, "Global communication and memory optimizing transformations for low power signal processing systems", IEEE workshop on VLSI signal processing, La Jolla CA, Oct. 1994. Also in VLSI Signal Processing VII, J.Rabaey, P.Chau, J.Eldon (eds.), IEEE Press, New York, pp.178-187, 1994.
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IEEE Workshop on VLSI Signal Processing
, pp. 178-187
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Catthoor, F.1
Franssen, F.2
Wuytack, S.3
Nachtergaele, L.4
De Man, H.5
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8
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52549114724
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System-level transformations for low power data transfer and storage
-
(eds. A.Chandrakasan, R.Brodersen), IEEE Press
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F.Catthoor, S.Wuytack, E.De Greef, F.Franssen, L.Nachtergaele. H.De Man, "System-level transformations for low power data transfer and storage", in paper collection on "Low power CMOS design" (eds. A.Chandrakasan, R.Brodersen), IEEE Press, pp.609-618, 1998.
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Paper Collection on "Low Power CMOS Design
, pp. 609-618
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Catthoor, F.1
Wuytack, S.2
De Greef, E.3
Franssen, F.4
Nachtergaele, L.5
De Man, H.6
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9
-
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0029255524
-
Gigachips: Deliver affordable digital multi-media for work and play via broadband network and set-top box
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(President Personal Productivity Products, Texas Instruments)., San Francisco CA, Feb.
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P.Chatterjee (President Personal Productivity Products, Texas Instruments), "Gigachips: deliver affordable digital multi-media for work and play via broadband network and set-top box", Plenary paper in Proc. IEEE Int. Solid-State Circ. Conf., San Francisco CA, pp.26-30, Feb. 1995.
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Plenary Paper in Proc. IEEE Int. Solid-State Circ. Conf
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Chatterjee, P.1
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11
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0030706516
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System level memory optimization for hardware-software co-design
-
Braunschweig, Germany, March
-
K.Danckaert, F.Catthoor, H.De Man, "System level memory optimization for hardware-software co-design", Proc. IEEE Intnl. Workshop on Hardware/Software Co-design, Braunschweig, Germany, pp.55-59, March 1997.
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Proc. IEEE Intnl. Workshop on Hardware/Software Co-design
, pp. 55-59
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Danckaert, K.1
Catthoor, F.2
De Man, H.3
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12
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0029474262
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Memory organization for video algorithms on programmable signal processors
-
Austin TX, Oct.
-
E.De Greef, F.Catthoor, H.De Man, "Memory organization for video algorithms on programmable signal processors", Proc. IEEE Int. Conf. on Computer Design, Austin TX, pp.552-557, Oct. 1995.
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(1995)
Proc. IEEE Int. Conf. on Computer Design
, pp. 552-557
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De Greef, E.1
Catthoor, F.2
De Man, H.3
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13
-
-
0003157633
-
Memory size reduction through storage order optimization for embedded parallel multimedia applications
-
Geneva, Switzerland, April
-
E.De Greef, F.Catthoor, H.De Man, "Memory Size Reduction through Storage Order Optimization for Embedded Parallel Multimedia Applications", Intnl. Parallel Proc. Symp.(IPPS) in Proc. Workshop on "Parallel Processing and Multimedia", Geneva, Switzerland, pp.84-98, April 1997.
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Intnl. Parallel Proc. Symp.(IPPS) in Proc. Workshop on "Parallel Processing and Multimedia
, pp. 84-98
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De Greef, E.1
Catthoor, F.2
De Man, H.3
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14
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0030690709
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Formalized methodology for data reuse exploration in hierarchical memory mappings
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Aug.
-
J.P.Diguet, S.Wuytack, F.Catthoor, H.De Man, "Formalized methodology for data reuse exploration in hierarchical memory mappings", Proc. IEEE Intnl. Symp. on Low Power Design, Monterey, pp.30-35, Aug. 1997.
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Proc. IEEE Intnl. Symp. on Low Power Design, Monterey
, pp. 30-35
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Diguet, J.P.1
Wuytack, S.2
Catthoor, F.3
De Man, H.4
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15
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0030243819
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Energy dissipation in general-purpose microprocessors
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Sep.
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R.Gonzales, M.Horowitz, "Energy dissipation in general-purpose microprocessors", IEEE J. Solid-state Circ., Vol.SC-31, No.9, pp.1277-1283, Sep. 1996.
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IEEE J. Solid-state Circ.
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, pp. 1277-1283
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Gonzales, R.1
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16
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33749979849
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Digital Video Coding at Telenor R &D Version 3.1
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Digital Video Coding at Telenor R &D, "Telenor's H.263 Software", Version 3.1, http://www.nta.no/brukere/DVC/h263 software/.
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Telenor's h.263 Software
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17
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0029288557
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Trends in low-power ram circuit technologies
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April
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K.Itoh, K.Sasaki, Y.Nakagome, "Trends in low-power RAM circuit technologies", special issue on "Low power electronics" of the Proceedings of the IEEE, Vol.83, No.4, pp.524-543, April 1995.
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Special Issue on "Low Power Electronics of the Proceedings of the IEEE
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Itoh, K.1
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Nakagome, Y.3
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18
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0028565177
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Minimization of memory traffic in high-level synthesis
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San Diego, CA, June
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D.Kolson, A.Nicolau, N.Dutt, "Minimization of memory traffic in high-level synthesis", Proc. 31st ACM/IEEE Design Automation Conf., San Diego, CA, pp.149-154, June 1994.
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Proc. 31st ACM/IEEE Design Automation Conf.
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Kolson, D.1
Nicolau, A.2
Dutt, N.3
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19
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0027799223
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Allocation of multiport memories for hierarchical data streams
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Santa Clara CA, Nov.
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P.Lippens, J.van Meerbergen, W.Verhaegh, A.van der Werf, "Allocation of multiport memories for hierarchical data streams", Proc. IEEE Int. Conf. Comp. Aided Design, Santa Clara CA, Nov. 1993.
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Proc. IEEE Int. Conf. Comp. Aided Design
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Lippens, P.1
Van Meerbergen, J.2
Verhaegh, W.3
Werf Der A.Van4
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20
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0029217509
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A chip set architecture for programmable real-time mpeg2 video encoder
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May., Santa Clara CA
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T.Matsumura et al., "A chip set architecture for programmable real-time MPEG2 video encoder", Proc. IEEE Custom Integrated Circuits Conf., Santa Clara CA, pp.393-396, May 1995.
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Proc. IEEE Custom Integrated Circuits Conf
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Matsumura, T.1
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21
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0029290289
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Portable video-ondemand in wireless communication
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April
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T.H.Meng, B.Gordon, E.Tsern, A.Hung, "Portable video-ondemand in wireless communication", special issue on "Low power electronics" of the Proceedings of the IEEE, Vol.83, No.4, pp.659-680, April 1995.
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Special Issue on "Low Power Electronics of the Proceedings of the IEEE
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Meng, T.H.1
Gordon, B.2
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22
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0029698677
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A 1v 1mb sram for portable equipment
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Aug.
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H.Morimura, N.Shibata, "A 1V 1MB SRAM for portable equipment", Proc. IEEE Intnl. Symp. on Low Power Design, Monterey, pp.61-66, Aug. 1996.
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, pp. 61-66
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Morimura, H.1
Shibata, N.2
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23
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0031070399
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Parallel processing ram chip with 256 mb dram and quad processors
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San Francisco CA, Feb.
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K.Murakami, S.Shirakawa, H.Miyajima, "Parallel processing RAM chip with 256 Mb DRAM and quad processors", Proc. IEEE Int. Solid-State Circ. Conf., San Francisco CA, pp.228-229, Feb. 1997.
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Shirakawa, S.2
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0030407483
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Low power storage exploration for h263 video decoder
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W.Burleson, K.Konstantinides, T.Meng, (eds.), IEEE Press, New York
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L.Nachtergaele, F.Catthoor, B.Kapoor, D.Moolenaar, S.Janssens, "Low power storage exploration for H.263 video decoder", IEEE workshop on VLSI signal processing, Monterey CA, Oct. 1996. Also in VLSI Signal Processing IX, W.Burleson, K.Konstantinides, T.Meng, (eds.), IEEE Press, New York, pp.116-125, 1996.
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IEEE Workshop on VLSI Signal Processing, Monterey CA, Oct. 1996. Also in VLSI Signal Processing IX
, pp. 116-125
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Nachtergaele, L.1
Catthoor, F.2
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Moolenaar, D.4
Janssens, S.5
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25
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0031997237
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System-level power optimization of video codecs on embedded cores a systematic approach
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Kluwer, Boston, Feb.
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L.Nachtergaele, D.Moolenaar, B.Vanhoof, F.Catthoor, H.De Man, "System-level power optimization of video codecs on embedded cores: a systematic approach", accepted for special issue on Future directions in the design and implementation of DSP systems (eds.Wayne Burleson, Konstantinos Konstantinides) of Journal of VLSI Signal Processing, Kluwer, Boston, Feb. 1998.
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Accepted for Special Issue on Future Directions in the Design and Implementation of DSP Systems (Eds.Wayne Burleson, Konstantinos Konstantinides) of Journal of VLSI Signal Processing
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Nachtergaele, L.1
Moolenaar, D.2
Vanhoof, B.3
Catthoor, F.4
De Man, H.5
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26
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0029216964
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A single chip 5 gops macroblock-level pixel processor for mpeg2 real-time encoding
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May., Santa Clara CA
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S.Nakagawa et al., "A single chip 5 GOPS macroblock-level pixel processor for MPEG2 real-time encoding", Proc. IEEE Custom Integrated Circuits Conf., Santa Clara CA, pp.397-400, May 1995.
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Proc. IEEE Custom Integrated Circuits Conf
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Nakagawa, S.1
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27
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0031074718
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A 500 mhz 4mb cmos pipeline-burst cache sram with point-to-point noise reduction coding i/o
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San Francisco CA, Feb.
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K.Nakamura, et al., "A 500 MHz 4Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O", Proc. IEEE Int. Solid-State Circ. Conf., San Francisco CA, pp.406-407, Feb. 1997.
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Proc. IEEE Int. Solid-State Circ. Conf.
, pp. 406-407
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Nakamura, K.1
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0030394812
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Memory data organization for improved cache performance in embedded processor applications
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La Jolla CA, Nov.
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P.R.Panda, N.D.Dutt, A.Nicolau, " Memory data organization for improved cache performance in embedded processor applications", Proc. 9th ACM/IEEE Intnl. Symp. on System-Level Synthesis, La Jolla CA, pp.90-95, Nov. 1996.
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, pp. 90-95
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Panda, P.R.1
Dutt, N.D.2
Nicolau, A.3
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0031073176
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Intelligent ram(iram): Chips that remember and compute
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San Francisco CA, Feb.
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D.A.Patterson et al., "Intelligent RAM(IRAM): chips that remember and compute", Proc. IEEE Int. Solid-State Circ. Conf., San Francisco CA, pp.224-225, Feb. 1997.
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Patterson, D.A.1
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VLSI architectures for video compression-A survey
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System-level power estimation and optimization-challenges and perspectives
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Rabaey, J.1
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0030083495
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Architecture and applications of the hipar video signal processor
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K.Roenner, J.Kneip, "Architecture and applications of the HiPar video signal processor", to appear in IEEE Trans. on Circuits and Systems for Video Technology, special issue on "VLSI for video signal processors" (eds. B.Ackland, T.Nishitani, P.Pirsch), 1996.
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To Appear in IEEE Trans. on Circuits and Systems for Video Technology, Special Issue on "VLSI for Video Signal Processors
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Roenner, K.1
Kneip, J.2
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0344006002
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Integrated memory ups speed, saves power
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I.Saeed, "Integrated memory ups speed, saves power", Electronic Engineering Times, pp.94, April 28, 1997.
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Electronic Engineering Times
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Saeed, I.1
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35
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0027577076
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A 6-ns 1-mb cmos sram with latched sense amplifier
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Apr.
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T.Seki, E.Itoh, C.Furukawa, I.Maeno, T.Ozawa, H.Sano, N.Suzuki, "A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier", IEEE J. of Solid-state Circuits, Vol.SC-28, No.4, pp.478-483, Apr. 1993.
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Sano, H.6
Suzuki, N.7
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36
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0030701111
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Fast and extensive system-level memory exploration for atm applications
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Antwerp, Belgium, Sep.
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P.Slock, S.Wuytack, F.Catthoor, G.de Jong, "Fast and extensive system-level memory exploration for ATM applications", Proc. 10th ACM/IEEE Intnl. Symp. on System-Level Synthesis, Antwerp, Belgium, pp.74-81, Sep. 1997.
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Proc. 10th ACM/IEEE Intnl. Symp. on System-Level Synthesis
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Slock, P.1
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A 30 ns 256 mb dramwith a multi-divided array structure
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Power analysis of embedded software: A first step towards software power minimization
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Santa Clara CA, Nov.
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Tiwari, V.1
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0012111580
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Background memory management for the synthesis of algebraic algorithms on multi-processor dsp chips
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Munich, Germany, Aug.
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I.Verbauwhede, F.Catthoor, J.Vandewalle, H.De Man, "Background memory management for the synthesis of algebraic algorithms on multi-processor DSP chips", Proc. VLSI'89, Int. Conf. on VLSI, Munich, Germany, pp.209-218, Aug. 1989.
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Power exploration for data dominated video applications
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