Image processing on high-performance RISC systems

Proceedings of the IEEE

Volumn 84, Issue 7, 1996, Pages 917-930

  Baglietto, Pierpaolo ^a   Maresca, Massimo ^a   Migliardi, Mauro ^b   Zingirian, Nicola ^b  

^a UNIVERSITY OF GENOA   (Italy)

^b UNIVERSITY OF PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTATIONAL COMPLEXITY; COMPUTER PROGRAMMING; COMPUTER SOFTWARE; DATA STRUCTURES; HIGH LEVEL LANGUAGES; IMAGE PROCESSING; PARALLEL PROCESSING SYSTEMS; PASCAL (PROGRAMMING LANGUAGE); PERFORMANCE; PROGRAM COMPILERS;

INSTRUCTION LEVEL PARALLELISM; MACHINE CODE; MEMORY HIERARCHY; PROGRAMMING MODEL; REFERENCE SYSTEMS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0030193484     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.503295     Document Type: Article

References (46)

1. T. Amano et cil., "DRS: A workstation based document recognition system for text entry," IEEE Computer, vol. 25, no. 7, pp. 67-71, July 1992.
2. T. Asprey et al., "Performance features of the PA7100 microprocessor," IEEE Micro, pp. 22-35, June 1993.
3. D. H. Ballard and C. M. Brown, Computer Vision. Englewood Cliffs, NJ: Prentice-Hall, 1982.
4. M. Bertero, T. A. Poggio, and V. Torre, "Ill-posed problems in early vision," Proc. IEEE, vol. 76, pp. 869-889, Aug. 1988.
5. Digital Equip. Corp., Alpha Workstation Summary, Sept. 1995.
6. Digital Equip. Corp., DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors-Hardware Ref. Manual, 1994.
7. D. Dixit, "The SPEC benchmarks," Parallel Computing, vol. 17, no. 1, pp. 195-209, 1991.
8. J. J. Dongarra and Gentzcsh, Eds., Computer Benchmarks. Amsterdam: North-Holland, 1993.
9. K. Dowd, High Performance Computing. New York: O'Reilly Assoc., 1993.
10. T. J. Fountain, K. N. Matthew, and M. J. B. Duff, "The CLIP7A image processor," IEEE Trans. Patt. Anal, and Mach. Intel!., vol. 10, pp. 310-319, 1988.
11. D. Greenley et al., UltraSPARC: The Next Generation Superscalar 64-Bit SPARC, CompCon Spring 95, Mar. 1995.
12. J. Heinrich, MIPS R4000 Microprocessor Users's Manual, MIPS Technol., 1994.
13. J. L. Hennessy and D. A. Pattcrson, Computer Architecture: A Quantitative Approach. New York: Morgan Kauffman, 1990.
14. Hewlett Packard, HP 9000 Series 700 Models 735/125, Sept. 1995.
15. Hewlett Packard, PA-RISC I.I Architecture and Instruction Set Reference Manual, Feb. 1994.
16. W. D. Hillis, The Connection Machine. Cambridge, MA: MIT Press, 1985.
17. IBM Corp., RISC System/6000 Oven-lew, Sept. 1995.
18. ISO/IEC JTC1/SC29/WG11, Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbits/s, ISO/IEC CDUI72-2, 1993.
19. R. Jain, The Art of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling. New York: Wiley, 1991.
20. J. JàJà, Introduction to Parallel Algorithms. Reading, MA: Addison-Wesley, 1992.
21. G. Kacmarcik, Optimizing PowerPC Code. Reading, MA: Addison-Wesley, 1995.
22. B. G. L. Lee, "A new algorithm to compute the discrete cosine transform," IEEE Trans. Acoust., Speech, Signal Process., vol. ASSP-32, pp. 1243-1245, Dec. 1984.
23. D. Legall, "MPEG-A video compression standard for multimedia applications," Commun. ACM, vol. 34, no. 4, pp. 47-58, Apr. 1991.
24. M. Maresca and T. J. Fountain, Eds., "Special issue on massively parallel computers," Proc. IEEE, vol. 79, 1991.
25. M. Maresca and H. Li, "Morphological operations on mesh connected architectures: A generalized convolution algorithm," in Proc. IEEE Conf. Computer Vision and Patt. Recog., Miami Beach, FL, June 1986, pp. 199-304.
26. E. McLellan, "The alpha AXP architecture and 21064 processor," IEEE Micro, pp. 36-47, June 1993.
27. J. L. Potter, Ed., The Massively Parallel Processor. Boston: MIT Press, 1980.
28. W. K. Pratt, Digital Image Processing. New York: Wiley, 1991.
29. A. Puri and R. Aravind, "Motion-compensated video coding," IEEE Trans. Cire, and Syst. for Video Technol., vol. 1, no. 4, pp. 351-361, Dec. 1991.
30. K. R. Rao and P. Yip, Discrete Cosine Transform-Algorithms, Advantages, Applications. London: Academic, 1990.
31. A. Rosenfeld and A. C. Kak, Digital Picture Processing. New York: Academic, 1982.
32. R. H. Saavedra and A. J. Smith, "Performance charcterization of optimizing compilers," IEEE Trans. Software Engineering, vol. 21, pp. 615-628, July 1995.
33. "Measuring cache and TLB performance and their effect on Benchmark runtimes," IEEE Trans. Computers, vol. 44, pp. 1223-1235, Oct. 1995.
34. Silicon Graphics Inc., Product Oven-lew, Sept. 1995.
35. Indigo2 and Power Indigo Techn. Rep., 1994.
36. S. P. Song, M. Denman, and J. Chang, "The PowerPC 604 RISC microprocessor," IEEE Micro, pp. 8-17, Oct. 1994.
37. SPARC Int. Inc., The SPARC Architecture Manual Version 8. Englewood Cliffs, NJ: Prentice-Hall, 1992.
38. R. M. Stallman, Using and Porting GNU CC, GNU Software Found., Sept. 1994.
39. SUN Microsystems, The SuperSPARC Microprocessor-White Paper, 1992.
40. Workstation Oven-iew, Sept. 1995.
41. M. Tremblay and P. Tirumalai, "Partners in platform design," IEEE Spectrum, vol. 32, no. 4, pp. 20-26, Apr. 1995.
42. L. Uhr, Ed., Multicomputer Vision. New York: Academic, 1988.
43. G. K. Wallace, "The JPEG still picture compression standard," Commun. ACM, vol. 34, no. 4, pp. 30-44, Apr. 1991.
44. C. C. Weems, "Architectural requirements of image understand-ing with respect to parallel processing," Proc. IEEE, vol. 79, pp. 537-547, Apr. 1991.
45. C. C. Weems, E. Riseman, A. Hanson, and A. Rosenfeld, "The DARPA image understanding Benchmark for parallel computers," J. Parallel and Distrib. Comput., vol. 11, pp. 1-24, 1991.
46. S. W. White, P. D. Hester, J. W. Kemp, and G. J. McWilliams, "How does processor performance MHz relate to end-user performance?," IEEE Micro, vol. 13, no. 4, pp. 8-16, Aug. 1993.