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Volumn 27, Issue 9, 2003, Pages 431-446

SPA - A secure Amulet core for smartcard applications

Author keywords

Amulet processor; Asynchronous processor; Asynchronous synthesis system; Self timed system; Smartcard security

Indexed keywords

PRODUCT DESIGN; PROGRAM PROCESSORS; SECURITY SYSTEMS; SMART CARDS;

EID: 0042827888     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(03)00093-0     Document Type: Conference Paper
Times cited : (16)

References (22)
  • 5
    • 0036173333 scopus 로고    scopus 로고
    • Balsa: An asynchronous hardware synthesis language
    • Edwards D., Bardsley A. Balsa: an asynchronous hardware synthesis language. Comput. J. 45:(1):2002;12-18.
    • (2002) Comput. J. , vol.45 , Issue.1 , pp. 12-18
    • Edwards, D.1    Bardsley, A.2
  • 6
    • 0003270928 scopus 로고
    • Handshake circuits - An asynchronous architecture for VLSI programming
    • Cambridge: Cambridge University Press
    • van Berkel K. Handshake circuits - An asynchronous architecture for VLSI programming, Cambridge International Series on Parallel Computers. vol. 5:1993;Cambridge University Press, Cambridge.
    • (1993) Cambridge International Series on Parallel Computers Computers , vol.5
    • Van Berkel, K.1
  • 9
    • 0034538423 scopus 로고    scopus 로고
    • Synthesising an asynchronous DMA controller with Balsa
    • Bardsley A., Edwards D.A. Synthesising an asynchronous DMA controller with Balsa. J. Syst. Architect. 46:2000;1309-1319.
    • (2000) J. Syst. Architect. , vol.46 , pp. 1309-1319
    • Bardsley, A.1    Edwards, D.A.2
  • 10
    • 85093467807 scopus 로고    scopus 로고
    • Design principles for tamper-resistant smartcard processors
    • Chicago, May
    • O. Kömmerling, M.G. Kuhn, Design principles for tamper-resistant smartcard processors, USENIX Workshop on Smartcard Technology, Chicago, May 1999, pp. 9-20.
    • (1999) USENIX Workshop on Smartcard Technology , pp. 9-20
    • Kömmerling, O.1    Kuhn, M.G.2
  • 14
    • 0027677633 scopus 로고
    • Delay-insensitive multi-ring structures, integration
    • Sparsø J., Staunstrup J. Delay-insensitive multi-ring structures, Integration. VLSI J. 15:(3):1993;313-340.
    • (1993) VLSI J. , vol.15 , Issue.3 , pp. 313-340
    • Sparsø, J.1    Staunstrup, J.2
  • 15
    • 0003185688 scopus 로고
    • La cryptographie militaire
    • Kerckhoffs A. La cryptographie militaire. J. Sci. Militaires. 9:1883;5-38.
    • (1883) J. Sci. Militaires , vol.9 , pp. 5-38
    • Kerckhoffs, A.1
  • 16
    • 0002349535 scopus 로고    scopus 로고
    • Modelling and simulation of asynchronous systems using the LARD hardware description language
    • Manchester, June
    • P.B. Endecott, S.B. Furber, Modelling and simulation of asynchronous systems using the LARD hardware description language, Proceedings of the 12th European Simulation Multiconference, Manchester, June 1998, pp. 39-43.
    • (1998) Proceedings of the 12th European Simulation Multiconference , pp. 39-43
    • Endecott, P.B.1    Furber, S.B.2
  • 18
    • 0042272959 scopus 로고    scopus 로고
    • On-chip timing reference for self-timed microprocessor
    • Temple S., Furber S.B. On-chip timing reference for self-timed microprocessor. IEE Electron. Lett. 36:(11):2000;942-943.
    • (2000) IEE Electron. Lett. , vol.36 , Issue.11 , pp. 942-943
    • Temple, S.1    Furber, S.B.2
  • 20
    • 0036761283 scopus 로고    scopus 로고
    • Chain: A delay-insensitive chip area interconnect
    • Bainbridge W.J., Furber S.B. Chain: a delay-insensitive chip area interconnect. IEEE Micro. 22:(5):2002;16-23.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 16-23
    • Bainbridge, W.J.1    Furber, S.B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.