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Volumn , Issue , 2013, Pages 294-297

Computation using mismatch: Neuromorphic extreme learning machines

Author keywords

[No Author keywords available]

Indexed keywords

CLASSIFICATION TASKS; DIGITAL IMPLEMENTATION; EXTREME LEARNING MACHINE; FIELD PROGRAMMABLE ANALOG ARRAYS; PROOF OF CONCEPT; SPICE SIMULATIONS; SYSTEM SIMULATIONS; VECTOR-MATRIX MULTIPLICATIONS;

EID: 84893561481     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BioCAS.2013.6679697     Document Type: Conference Paper
Times cited : (12)

References (11)
  • 1
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    • A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity
    • Jan
    • G. Indiveri, E. Chicca, and R. Douglas, "A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity," IEEE Transactions on Neural Networks, vol. 17, no. 1, pp. 211-221, Jan. 2006.
    • (2006) IEEE Transactions on Neural Networks , vol.17 , Issue.1 , pp. 211-221
    • Indiveri, G.1    Chicca, E.2    Douglas, R.3
  • 2
    • 78149468320 scopus 로고    scopus 로고
    • Nullcline based Design of a Silicon Neuron
    • Nov
    • A. Basu and P. Hasler, "Nullcline based Design of a Silicon Neuron," IEEE Transactions on Circuits and Systems I, vol. 57, no. 11, pp. 2938-47, Nov. 2010.
    • (2010) IEEE Transactions on Circuits and Systems I , vol.57 , Issue.11 , pp. 2938-2947
    • Basu, A.1    Hasler, P.2
  • 3
    • 84875055083 scopus 로고    scopus 로고
    • A Learning-enabled Neuron Array IC Based upon Transistor Channel Models of Biological Phenomenon
    • Feb
    • S. Brink, S. Nease, and P. Hasler et al., "A Learning-enabled Neuron Array IC Based upon Transistor Channel Models of Biological Phenomenon," IEEE Transactions on Biomedical Circuits and Systems, vol. 7, no. 1, pp. 71-81, Feb. 2012.
    • (2012) IEEE Transactions on Biomedical Circuits and Systems , vol.7 , Issue.1 , pp. 71-81
    • Brink, S.1    Nease, S.2    Hasler, P.3
  • 4
    • 79952423693 scopus 로고    scopus 로고
    • A device mismatch compensation method for VLSI neural networks
    • E. Neftci and G. Indiveri, "A device mismatch compensation method for VLSI neural networks," IEEE Biomedical Circuits and Systems, pp. 262-265, 2010.
    • (2010) IEEE Biomedical Circuits and Systems , pp. 262-265
    • Neftci, E.1    Indiveri, G.2
  • 6
    • 84870252936 scopus 로고    scopus 로고
    • Silicon Spiking Neurons for Hardware Implementation of Extreme Learning Machines
    • A. Basu, S. Shuo, H. Zhou, M. H. Lim, and G. B. Huang, "Silicon Spiking Neurons for Hardware Implementation of Extreme Learning Machines," Neurocomputing, vol. 102, pp. 125-34, 2012.
    • (2012) Neurocomputing , vol.102 , pp. 125-134
    • Basu, A.1    Shuo, S.2    Zhou, H.3    Lim, M.H.4    Huang, G.B.5
  • 7
    • 77950193145 scopus 로고    scopus 로고
    • A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System
    • April
    • N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. Chandrakasan, "A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 804-16, April 2010.
    • (2010) IEEE Journal of Solid-State Circuits , vol.45 , Issue.4 , pp. 804-816
    • Verma, N.1    Shoeb, A.2    Bohorquez, J.3    Dawson, J.4    Guttag, J.5    Chandrakasan, A.6
  • 9
    • 34247503687 scopus 로고    scopus 로고
    • A Sub-microwatt Analog VLSI Trainable Pattern Classifier
    • May
    • S. Chakrabartty and G. Cauwenberghs, "A Sub-microwatt Analog VLSI Trainable Pattern Classifier," IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1169-1179, May 2007.
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.5 , pp. 1169-1179
    • Chakrabartty, S.1    Cauwenberghs, G.2
  • 10
    • 84871724333 scopus 로고    scopus 로고
    • Scaling Energy Per Operation via an Asynchronous Pipeline
    • Jan
    • B. Marr, B. Degnan, P. E. Hasler, and D. Anderson, "Scaling Energy Per Operation via an Asynchronous Pipeline," IEEE Transactions on VLSI, vol. 21, no. 1, pp. 147-151, Jan. 2013.
    • (2013) IEEE Transactions on VLSI , vol.21 , Issue.1 , pp. 147-151
    • Marr, B.1    Degnan, B.2    Hasler, P.E.3    Anderson, D.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.