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1
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33244465845
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A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity
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Jan
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G. Indiveri, E. Chicca, and R. Douglas, "A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity," IEEE Transactions on Neural Networks, vol. 17, no. 1, pp. 211-221, Jan. 2006.
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IEEE Transactions on Neural Networks
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Indiveri, G.1
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Nullcline based Design of a Silicon Neuron
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Nov
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A. Basu and P. Hasler, "Nullcline based Design of a Silicon Neuron," IEEE Transactions on Circuits and Systems I, vol. 57, no. 11, pp. 2938-47, Nov. 2010.
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IEEE Transactions on Circuits and Systems I
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Basu, A.1
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84875055083
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A Learning-enabled Neuron Array IC Based upon Transistor Channel Models of Biological Phenomenon
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Feb
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S. Brink, S. Nease, and P. Hasler et al., "A Learning-enabled Neuron Array IC Based upon Transistor Channel Models of Biological Phenomenon," IEEE Transactions on Biomedical Circuits and Systems, vol. 7, no. 1, pp. 71-81, Feb. 2012.
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IEEE Transactions on Biomedical Circuits and Systems
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Brink, S.1
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79952423693
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A device mismatch compensation method for VLSI neural networks
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E. Neftci and G. Indiveri, "A device mismatch compensation method for VLSI neural networks," IEEE Biomedical Circuits and Systems, pp. 262-265, 2010.
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(2010)
IEEE Biomedical Circuits and Systems
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Neftci, E.1
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5
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84859007933
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Extreme Learning Machine for Regression and Multiclass Classification
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G.-B. Huang, H. Zhou, X. Ding, and R. Zhang, "Extreme Learning Machine for Regression and Multiclass Classification," IEEE Trans. on Systems, Man and Cybernetics- part B, vol. 42, no. 2, pp. 515-29, 2012.
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IEEE Trans. On Systems, Man and Cybernetics- Part B
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84870252936
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Silicon Spiking Neurons for Hardware Implementation of Extreme Learning Machines
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A. Basu, S. Shuo, H. Zhou, M. H. Lim, and G. B. Huang, "Silicon Spiking Neurons for Hardware Implementation of Extreme Learning Machines," Neurocomputing, vol. 102, pp. 125-34, 2012.
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Neurocomputing
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7
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77950193145
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A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System
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April
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N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. Chandrakasan, "A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 804-16, April 2010.
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8
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79958178274
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Extreme Learning Machines: A Survey
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G.-B. Huang, D. H. Wang, and Y. Lan, "Extreme Learning Machines: A Survey," Int. J. Mach. Learn. & Cyber., vol. 2, pp. 107-122, 2011.
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Huang, G.-B.1
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9
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34247503687
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A Sub-microwatt Analog VLSI Trainable Pattern Classifier
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May
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S. Chakrabartty and G. Cauwenberghs, "A Sub-microwatt Analog VLSI Trainable Pattern Classifier," IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1169-1179, May 2007.
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IEEE Journal of Solid-State Circuits
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Chakrabartty, S.1
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10
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84871724333
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Scaling Energy Per Operation via an Asynchronous Pipeline
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Jan
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B. Marr, B. Degnan, P. E. Hasler, and D. Anderson, "Scaling Energy Per Operation via an Asynchronous Pipeline," IEEE Transactions on VLSI, vol. 21, no. 1, pp. 147-151, Jan. 2013.
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IEEE Transactions on VLSI
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Marr, B.1
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11
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57849085788
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RASP 2.8: A New Generation of Floating-gate based Field Programmable Analog Array
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A. Basu, C. Twigg, S. Brink, and P. Hasler et al, "RASP 2.8: A New Generation of Floating-gate based Field Programmable Analog Array," in Proceedings of the IEEE Custom Integrated Circuits Conference, Sept. 2008, pp. 213-16.
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Proceedings of the IEEE Custom Integrated Circuits Conference, Sept. 2008
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Basu, A.1
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