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Volumn , Issue , 2013, Pages 1893-1900

Communication pipelining for code generation from simulink models

Author keywords

communication pipeline; thread switching; SCCbased algorithm; repartition

Indexed keywords

CODE GENERATION; COMMUNICATION COST; CYCLIC TOPOLOGY; DISTRIBUTED MEMORY; FUNCTIONAL TASKS; PARALLEL EXECUTIONS; PIPELINE TECHNIQUES; SIMULINK MODELS;

EID: 84893458522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TrustCom.2013.251     Document Type: Conference Paper
Times cited : (4)

References (13)
  • 1
    • 15044358802 scopus 로고    scopus 로고
    • Hardware/software interface codesign for embedded systems
    • A. A. Jerraya and W. Wolf, "Hardware/software interface codesign for embedded systems," IEEE Computer, vol. 38, no. 2, pp. 63-69, 2005.
    • (2005) IEEE Computer , vol.38 , Issue.2 , pp. 63-69
    • Jerraya, A.A.1    Wolf, W.2
  • 4
    • 84893470868 scopus 로고    scopus 로고
    • "Rti-mp," http://www.dspaceinc.com/ww/en/inc/home/products/sw/ impsw/rtimpblo.cfm.
    • Rti-mp
  • 6
    • 33748631005 scopus 로고    scopus 로고
    • Functional modeling techniques for efficient sw code generation of video codec applications
    • S.-I. Han, S.-I. Chae, and A. A. Jerraya, "Functional modeling techniques for efficient sw code generation of video codec applications," in ASP-DAC, 2006, pp. 935-940.
    • (2006) ASP-DAC , pp. 935-940
    • Han, I.S.1    Chae, I.S.2    Jerraya, A.A.3
  • 7
    • 34548023073 scopus 로고    scopus 로고
    • Reducing fine-grain communication overhead in multithread code generation for heterogeneous mpsoc
    • L. Brisolara, S.-i. Han, X. Guerin, L. Carro, R. Reis, S.-I. Chae, and A. Jerraya, "Reducing fine-grain communication overhead in multithread code generation for heterogeneous mpsoc," in SCOPES, 2007, pp. 81-89.
    • (2007) SCOPES , pp. 81-89
    • Brisolara, L.1    Han, I.S.2    Guerin, X.3    Carro, L.4    Reis, R.5    Chae, I.S.6    Jerraya, A.7
  • 8
    • 34547150218 scopus 로고    scopus 로고
    • Buffer memory optimization for video codec application modeled in simulink
    • S.-I. Han, X. Guerin, S.-I. Chae, and A. A. Jerraya, "Buffer memory optimization for video codec application modeled in simulink," in DAC, 2006, pp. 689-694.
    • (2006) DAC , pp. 689-694
    • Han, I.S.1    Guerin, X.2    Chae, I.S.3    Jerraya, A.A.4
  • 9
    • 4444343175 scopus 로고    scopus 로고
    • An efficient scalable and flexible data transfer architecture for multiprocessor soc with massive distributed memory
    • S.-I. Han, A. Baghdadi, M. Bonaciu, S.-I. Chae, and A. A. Jerraya, "An efficient scalable and flexible data transfer architecture for multiprocessor soc with massive distributed memory," in DAC, 2004, pp. 250-255.
    • (2004) DAC , pp. 250-255
    • Han, I.S.1    Baghdadi, A.2    Bonaciu, M.3    Chae, I.S.4    Jerraya, A.A.5
  • 10
    • 0001790593 scopus 로고
    • Depth-first search and linear graph algorithms
    • R. Tarjan, "Depth-first search and linear graph algorithms," SIAM Journal on Computing, vol. 1, no. 2, pp. 146-160, 1972.
    • (1972) SIAM Journal on Computing , vol.1 , Issue.2 , pp. 146-160
    • Tarjan, R.1
  • 11
    • 58149129333 scopus 로고    scopus 로고
    • Simulinkr-based heterogeneous multiprocessor soc design flow for mixed hardware/software refinement and simulation
    • S.-I. Han, S.-I. Chae, L. B. de Brisolara, L. Carro, K. Popovici, X. Guerin, A. A. Jerraya, K. Huang, L. Li, and X. Yan, "SimulinkR-based heterogeneous multiprocessor soc design flow for mixed hardware/software refinement and simulation," Integration, vol. 42, no. 2, pp. 227-245, 2009.
    • (2009) Integration , vol.42 , Issue.2 , pp. 227-245
    • Han, I.S.1    Chae, I.S.2    De Brisolara, L.B.3    Carro, L.4    Popovici, K.5    Guerin, X.6    Jerraya, A.A.7    Huang, K.8    Li, L.9    Yan, X.10


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.