Low-complexity welch power spectral density computation

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 61, Issue 1, 2014, Pages 172-182

  Parhi, Keshab K ^a   Ayinala, Manohar ^a,b  

^a University of Minnesota   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

FFT; fractional delay filter; frequency domain convolution; low complexity; low power; power spectral density; Welch method; windowing

Indexed keywords

CONVOLUTION; COST BENEFIT ANALYSIS; FAST FOURIER TRANSFORMS; FIR FILTERS; FREQUENCY DOMAIN ANALYSIS; PASSIVE FILTERS; POWER SPECTRAL DENSITY; SPECTRAL DENSITY;

FRACTIONAL DELAY FILTERS; FREQUENCY DOMAINS; LOW POWER; LOW-COMPLEXITY; WELCH METHOD; WINDOWING;

COMPUTATIONAL COMPLEXITY;

EID: 84892594837     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2013.2264711     Document Type: Article

References (26)

1. P. Stoica and R. L. Moses, Introduction to Spectral Analysis. Englewood Cliffs, NJ, USA: Prentice-Hall, 1997.
2. M. Hayes, Statistical Digital Signal Processing and Modeling. New York, NY, USA: Wiley, 1996.
3. F. El-Hawary and T. Richards, "A systolic computer architecture for spectrum analysis," Proc. OCEANS, vol. 4, pp. 1061-1065, Sep. 1989. (Pubitemid 20678035)
4. T.-H. Yu, C.-H. Yang, D. Cabric, and D. Markovic, "A 7.4 mW 200 MS/s wideband spectrum sensing digital baseband processor for cognitive radios," in Proc. Symp. VLSI Circuits, Jun. 2011, pp. 254-255.
5. T. Yucek and H. Arslan, "A survey of spectrum sensing algorithms for cognitive radio applications," IEEE Commun. Surveys Tutorials, vol. 11, no. 1, pp. 116-130, 2009.
6. Y. Park, L. Luo, K. K. Parhi, and T. Netoff, "Seizure prediction with spectral power of EEG using cost-sensitive support vector machines," Epilepsia, vol. 52, no. 10, pp. 1761-1770, Oct. 2011.
7. A. Oppenheim and R. Schafer, Discrete Time Signal Processing, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall.
8. S. Haykin, Adaptive Filter Theory, 4th ed. Englewood Cliffs, NJ, USA: Prentice-Hall.
9. P. D. Welch, "The use of fast fourier transform for the estimation of power spectra: A method based on time averaging over short, modified periodograms," IEEE Trans. Audio Electroacoustics, vol. AU-15, pp. 70-73, Jun. 1967.
10. S. Zhang, D. Yu, and S. Sheng, "A discrete STFT processor for realtime spectrum analysis," in Proc. IEEE Asia Pacific Conf. Circuits Syst., 2006, pp. 1943-1946.
11. A. Sanchez, M. Garrido, L. Vallejo, J. Grajal, and C. Lopez-Barrio, "Digital channelised receivers on FPGAs platforms," in Proc. IEEE Int. Radar Conf., 2005, pp. 816-821.
12. F. J. Harris, "On the use of windows for harmonic analysis with the discrete Fourier transform," Proc. IEEE, vol. 66, pp. 51-83, 1978. (Pubitemid 8338069)
13. T. I. Laakso, V. Valimaki, M. Karjalainen, and U. K. Laine, "Splitting the unit delay [FIR/all pass filters design]," IEEE Signal Processing Magazine, vol. 13, no. 1, pp. 30-60, Jan. 1996. (Pubitemid 126518972)
14. E. Hermanowicz, "Explicit formulas for weighing coefficients of maximally flat tunable FIR delayers," Electron. Letters, vol. 28, no. 20, pp. 1936-1937, Sept. 1992. (Pubitemid 23571690)
15. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. Hoboken, NJ, USA: Wiley, 1999.
16. Freiburg EEG Database [Online]. Available: https://epilepsy.unifreiburg. de/freiburg-seizureprediction-project/eeg-database
17. V. Sundararajan and K. K. Parhi, "A novel multiply multiple accumulator component for low power PDSP design," in Proc. IEEE Int. Conf. Acoustics, Speech Signal Process., Jun. 2000, vol. 6, pp. 3247-3250.
18. S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi, CACTI 5, Advanced Architecture Laboratory HP Laboratories HPL-2007-167, 2007 [Online]. Available: http://www.hpl.hp.com/techreports/2008/HPL-200820.html
19. M. Shin and H. Lee, "A high-speed four parallel radix-24 FFT/IFFT processor for UWB applications," in Proc. IEEE ISCAS 2008, May 2008, pp. 960-963.
20. M. Ayinala, M. Brown, and K. K. Parhi, "Pipelined parallel FFT architectures via folding transformation," IEEE Trans. VLSI Syst., vol. 20, no. 6, pp. 1068-1081, June 2012.
21. T. Cho, H. Lee, J. Park, and C. Park, "A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications," in Proc. ISCAS, 2011, pp. 1259-1262.
22. Z. Wang, L. G. Yeo, W. Li, Y. Yan, Y. Ting, and M. Tomisawa, "A novel FFT processor for OFDM UWB systems," in Proc. IEEE APCCAS, Dec. 2006, pp. 374-377.
23. S. Qiao, Y. Hei, B.Wu, and Y. Zhou, "An area and power efficient FFT processor for UWB systems," in Proc. IEEE WICOM, Sept. 2007, pp. 582-585.
24. S.-N. Tang, J. Tsai, and T.-Y. Chang, "A 2.4-GS/s FFT processor for OFDM-based WPAN applications," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 451-455, Jun. 2010.
25. M. Garrido, K. K. Parhi, and J. Grajal, "A pipelined FFT architecture for real-valued signals," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 12, pp. 2634-2643, Dec. 2009.
26. M. Ayinala and K. K. Parhi, "FFT architectures for real-valued signals based on radix-23 and radix-24 algorithms," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, 2013.