A novel multiply multiple accumulator component for low power PDSP design

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 6, Issue , 2000, Pages 3247-3250

  Sundararajan, Vijay ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSORS; FIR FILTERS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; MULTIPLYING CIRCUITS; SWITCHING CIRCUITS; VLSI CIRCUITS;

ASSOCIATED MEMORY; FILTER OPERATIONS; LOW POWER; LOW POWER SCHEDULING; MULTIPLY ACCUMULATORS; SWITCHING ACTIVITIES;

SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSING;

LOW POWER MAPPING; MULTIPLY MULTIPLE ACCUMULATOR COMPONENT; POWER CONSUMPTION; PROGRAMMABLE DIGITAL SIGNAL PROCESSOR;

EID: 0033693952     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2000.860092     Document Type: Conference Paper

References (9)

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