The TTEthernet synchronisation protocols and their formal verification

International Journal of Critical Computer-Based Systems

Volumn 4, Issue 3, 2013, Pages 280-300

  Steiner, Wilfried ^a   Dutertre, Bruno ^b  

^a TTTech North America   (Austria)

^b SRI INTERNATIONAL   (United States)

Author keywords

Clock synchronisation; Fault tolerance; Formal verification; Model checking; SAE AS6802; TTEthernet

Indexed keywords

EID: 84891361419     PISSN: 17578779     EISSN: 17578787     Source Type: Journal    
DOI: 10.1504/IJCCBS.2013.058398     Document Type: Article

References (23)

1. AEEC (2003) ARINC Project Paper 664, Aircraft Data Networks, Part7, AFDX Network (Draft), Aeronautic Radio, Inc., November.
2. Barsotti, D., Nieto, L. and Tiu, A. (2007) 'Verification of clock synchronization algorithms: Experiments on a combination of deductive tools', Formal Aspects of Computing, July, Vol. 19, No. 3, pp.321-341.
3. de Moura, L., Owre, S., Ruess, H., Rushby, J., Shankar, N., Sorea, M. and Tiwari, A. (2004) 'SAL 2', in Computer-Aided Verification, LNCS, Vol. 3114, pp.496-500, Springer.
4. de Moura, L., Rueß, H. and Sorea, M. (2003) 'Bounded model checking and induction: From refutation to verification', in Computer-Aided Verification, CAV 2003, Lecture Notes in Computer Science, Vol. 2725, pp.14-26, Springer.
5. Dutertre, B. and Sorea, M. (2004) 'Modeling and verification of a fault-tolerant real-time startup protocol using calendar automata', in Proc. of Formats/FTRTFT, Lecture Notes in Computer Science, Springer-Verlag, September, Vol. 3253, pp.199-214.
6. Dutertre, B., Shankar, N. and Owre, S. (2012) 'Integrated formal analysis of timed-triggered Ethernet', Contractor Report NASA/CR-2012-217554, NASA, March 2012, [online] http://ntrs.larc.nasa.gov/(accessed 26 June 2013).
7. Hoyme, H. and Driscoll, K. (1993) 'Safebus (tm)', IEEE Aerospace and Electronics Systems Magazine, March, Vol. 8, No. 3, pp.34-39.
8. Kopetz, H. (2002) TTP/C Protocol - Version 1.0. TTTech Computertechnik AG, Vienna, Austria, July [online] http://www.ttagroup.org/(accessed 26 June 2013).
9. Lamport, L. and Melliar-Smith, P.M. (1984) 'Byzantine clock synchronization', in Proc. of the 3rd annual ACM Symposium on Principles of Distributed Computing, ACM, New York, NY, USA, pp.68-74.
10. Lundelius, J. and Lynch, N. (1984) 'An upper and lower bound for clock synchronization', Information and Control, Vol. 62, Nos. 2-3, pp.190-204.
11. Malekpour, M.R. (2007) 'Model checking a byzantine-fault-tolerant self-stabilizing protocol for distributed clock synchronization systems', Technical Report NASA/TM-2007-215083, NASA.
12. Miner, P.S. (1993) Verification of Fault-Tolerant Clock Synchronization Systems, NASA Technical Paper 2249, NASA.
13. Pfeifer, H., Schwier, D. and von Henke, F.W. (1999) 'Formal verification for time-triggered clock synchronization', in Weinstock, C.B. and Rushby, J. (Eds.): Dependable Computing for Critical Applications 7, January, Vol. 12, pp.207-226, IEEE Computer Society.
14. Pike, L. (2007) 'Modeling time-triggered protocols and verifying their real-time schedules', in Proceedings of Formal Methods in Computer Aided Design (FMCAD'07), IEEE, pp.231-238.
15. Rushby, J. and von Henke, F. (1991) 'Formal verification of the interactive convergence clock synchronization algorithm', Technical Report SRI-CSL-89-3R, Computer Science Laboratory, SRI International, Menlo Park, CA, February 1989; Revised August 1991.
16. Schwier, D. and von Henke, F. (1998) 'Mechanical verification of clock synchronization algorithms', in Formal Techniques in Real-Time and Fault-Tolerant Systems, Lecture Notes in Computer Science, Vol. 1486, pp.262-271, Springer-Verlag.
17. Serafini, M., Bokor, P., Suri, N., Vinter, J., Ademaj, S., Brandstätter, W., Tagliabò, F. and Jens, K. (2011) 'Application-level diagnostic and membership protocols for generic timed-triggered systems', IEEE Transactions on Dependable and Secure Computing, March-April, Vol. 8, No. 2, pp.177-193.
18. Shankar, N. (1992) 'Mechanical verification of a generalized protocol for byzantine fault-tolerant clock synchronization', in Formal Techniques in Real-Time and Fault-Tolerant Systems, Lecture Notes in Computer Science, Vol. 571, pp.217-236, Springer-Verlag.
19. Steiner, W. (2009) 'TTEthernet executable formal specification', Deliverable 236701 for the CoMMiCS project1.
20. Steiner, W. and Dutertre, B. (2010) 'SMT-based formal verification of a TTEthernet synchronization function', in Formal Methods for Industrial Critical Systems, Lecture Notes in Computer Science, Vol. 6371, pp.148-163, Springer-Verlag.
21. Steiner, W. and Dutertre, B. (2011a) 'Automated formal verification of the TTethernet synchronization quality', in NASA Formal Methods (NFM'2011), Lecture Notes in Computer Science, Vol. 6617, pp.375-390, Springer-Verlag.
22. Steiner, W. and Dutertre, B. (2011b) 'Layered diagnosis and clock-rate correction for the TTethernet clock synchronization protocol', in PRDC 2011, pp.244-253.
23. Steiner, W. and Kopetz, H. (2006) 'The startup problem in fault-tolerant time-triggered communication', in Dependable Systems and Networks (DSN'2006), pp.35-44.