-
1
-
-
0141684229
-
The Time-Triggered Architecture
-
Kopetz, H., Bauer, G.: The Time-Triggered Architecture. Proceedings of the IEEE 91(1), 112-126 (2003)
-
(2003)
Proceedings of the IEEE
, vol.91
, Issue.1
, pp. 112-126
-
-
Kopetz, H.1
Bauer, G.2
-
2
-
-
79955037899
-
Orion avionics employ COTS technologies
-
June
-
Howard, C.E.: Orion avionics employ COTS technologies. In: Avionics Intelligence (June 2009)
-
(2009)
Avionics Intelligence
-
-
Howard, C.E.1
-
3
-
-
0021470560
-
An upper and lower bound for clock synchronization
-
Lundelius, J., Lynch, N.: An upper and lower bound for clock synchronization. Information and Control 62(2-3), 190-204 (1984)
-
(1984)
Information and Control
, vol.62
, Issue.2-3
, pp. 190-204
-
-
Lundelius, J.1
Lynch, N.2
-
5
-
-
20844437189
-
-
Vienna, Austria: TTTech Computertechnik AG July
-
Kopetz, H.: TTP/C Protocol - Version 1.0. Vienna, Austria: TTTech Computertechnik AG (July 2002), http://www.ttagroup.org
-
(2002)
TTP/C Protocol - Version 1.0
-
-
Kopetz, H.1
-
6
-
-
0003976812
-
-
Cornell University, Ithaca, NY, USA, Tech. Rep. TR87-859
-
Schneider, F.B.: Understanding protocols for byzantine clock synchronization. Cornell University, Ithaca, NY, USA, Tech. Rep. TR87-859 (1987)
-
(1987)
Understanding Protocols for Byzantine Clock Synchronization
-
-
Schneider, F.B.1
-
7
-
-
84934368731
-
-
Computer Science Laboratory, Menlo Park, CA, Tech. Rep. SRI-CSL-89-3R, February (revised online August 1991)
-
Rushby, J., von Henke, F.: Formal verification of the interactive convergence clock synchronization algorithm. Computer Science Laboratory, SRI International, Menlo Park, CA, Tech. Rep. SRI-CSL-89-3R, (February 1989), http://www.csl.sri.com/papers/csl-89-3/ (revised online August 1991)
-
(1989)
Formal Verification of the Interactive Convergence Clock Synchronization Algorithm
-
-
Rushby, J.1
Von Henke, F.2
-
8
-
-
85030310319
-
Mechanical verification of a generalized protocol for byzantine fault-tolerant clock synchronization
-
Vytopil, J. (ed.) FTRTFT 1992. Springer, Heidelberg
-
Shankar, N.: Mechanical verification of a generalized protocol for byzantine fault-tolerant clock synchronization. In: Vytopil, J. (ed.) FTRTFT 1992. LNCS, vol. 571, pp. 217-236. Springer, Heidelberg (1992)
-
(1992)
LNCS
, vol.571
, pp. 217-236
-
-
Shankar, N.1
-
9
-
-
0005889578
-
Verification of fault-tolerant clock synchronization systems
-
Miner, P.S.: Verification of fault-tolerant clock synchronization systems. NASA, NASA Technical Paper 2249 (1993), http://ntrs.nasa.gov
-
(1993)
NASA Technical Paper 2249
-
-
Miner, P.S.1
-
10
-
-
84958657477
-
Mechanical verification of clock synchronization algorithms
-
Ravn, A.P., Rischel, H. (eds.) FTRTFT 1998. Springer, Heidelberg
-
Schwier, D., von Henke, F.: Mechanical verification of clock synchronization algorithms. In: Ravn, A.P., Rischel, H. (eds.) FTRTFT 1998. LNCS, vol. 1486, pp. 262-271. Springer, Heidelberg (1998)
-
(1998)
LNCS
, vol.1486
, pp. 262-271
-
-
Schwier, D.1
Von Henke, F.2
-
11
-
-
84988985992
-
Formal verification for time-triggered clock synchronization
-
Weinstock, C.B., Rushby, J. (eds.) January
-
Pfeifer, H., Schwier, D., von Henke, F.: Formal verification for time-triggered clock synchronization. In: Weinstock, C.B., Rushby, J. (eds.) Dependable Computing for Critical Applications, vol. 7, pp. 206-226 (January 1999)
-
(1999)
Dependable Computing for Critical Applications
, vol.7
, pp. 206-226
-
-
Pfeifer, H.1
Schwier, D.2
Von Henke, F.3
-
12
-
-
34547541212
-
Verification of clock synchronization algorithms: Experiments on a combination of deductive tools
-
Barsotti, D., Nieto, L., Tiu, A.: Verification of clock synchronization algorithms: experiments on a combination of deductive tools. Formal Aspects of Computing 19, 321-341 (2007)
-
(2007)
Formal Aspects of Computing
, vol.19
, pp. 321-341
-
-
Barsotti, D.1
Nieto, L.2
Tiu, A.3
-
13
-
-
47249090848
-
Modeling time-triggered protocols and verifying their real-time schedules
-
IEEE, Los Alamitos
-
Pike, L.: Modeling time-triggered protocols and verifying their real-time schedules. In: Proceedings of Formal Methods in Computer Aided Design (FMCAD 2007), pp. 231-238. IEEE, Los Alamitos (2007)
-
(2007)
Proceedings of Formal Methods in Computer Aided Design (FMCAD 2007)
, pp. 231-238
-
-
Pike, L.1
-
14
-
-
77958073618
-
SMT-Based formal verification of a TTEthernet synchronization function
-
Kowalewski, S., Roveri, M. (eds.) FMICS 2010. Springer, Heidelberg
-
Steiner, W., Dutertre, B.: SMT-Based formal verification of a TTEthernet synchronization function. In: Kowalewski, S., Roveri, M. (eds.) FMICS 2010. LNCS, vol. 6371, pp. 148-163. Springer, Heidelberg (2010)
-
(2010)
LNCS
, vol.6371
, pp. 148-163
-
-
Steiner, W.1
Dutertre, B.2
-
16
-
-
14744281167
-
Tool presentation: SAL2
-
Alur, R., Peled, D.A. (eds.) CAV 2004. Springer, Heidelberg
-
de Moura, L., Owre, S., Rueß, H., Rushby, J., Shankar, N., Sorea, M., Tiwari, A.: Tool presentation: SAL2. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114. Springer, Heidelberg (2004)
-
(2004)
LNCS
, vol.3114
-
-
De Moura, L.1
Owre, S.2
Rueß, H.3
Rushby, J.4
Shankar, N.5
Sorea, M.6
Tiwari, A.7
-
17
-
-
29244482627
-
Bounded model checking and induction: From refutation to verification
-
Voronkov, A. (ed.) CAV 2003. Springer, Heidelberg
-
de Moura, L., Rueß, H., Sorea, M.: Bounded model checking and induction: From refutation to verification. In: Voronkov, A. (ed.) CAV 2003. LNCS, vol. 2725, pp. 14-26. Springer, Heidelberg (2003)
-
(2003)
LNCS
, vol.2725
, pp. 14-26
-
-
De Moura, L.1
Rueß, H.2
Sorea, M.3
-
18
-
-
35048826323
-
Modeling and verification of a fault-tolerant real-time startup protocol using calendar automata
-
Lakhnech, Y., Yovine, S. (eds.) FORMATS 2004 and FTRTFT 2004. Springer, Heidelberg
-
Dutertre, B., Sorea, M.: Modeling and verification of a fault-tolerant real-time startup protocol using calendar automata. In: Lakhnech, Y., Yovine, S. (eds.) FORMATS 2004 and FTRTFT 2004. LNCS, vol. 3253, pp. 199-214. Springer, Heidelberg (2004)
-
(2004)
LNCS
, vol.3253
, pp. 199-214
-
-
Dutertre, B.1
Sorea, M.2
|