Layered diagnosis and clock-rate correction for the TTEthernet clock synchronization protocol

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC

Volumn , Issue , 2011, Pages 244-253

  Steiner, Wilfried ^a   Dutertre, Bruno ^b  

^a TTTech North America   (Austria)

^b SRI INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDED MODEL; CLOCK SYNCHRONIZATION; CORRECTION ALGORITHMS; CYBER PHYSICAL SYSTEMS (CPSS); DATA TYPE; DIAGNOSIS ALGORITHMS; FAULT-TOLERANT; FORMAL DEVELOPMENT; FORMAL FRAMEWORK; FORMAL PROOFS; FORMAL VERIFICATIONS; MODEL CHECKER; REAL TIME; THEOREM PROVERS; TIME-TRIGGERED ARCHITECTURES;

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; MECHANICAL CLOCKS; MODEL CHECKING; NETWORK ARCHITECTURE;

ALGORITHMS;

EID: 84857775278     PISSN: 15410110     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2011.36     Document Type: Conference Paper

References (12)

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