Exploring ESD challenges in sub-20-nm bulk FinFET CMOS technology nodes

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2013, Pages

  Chen, Shih Hung ^a   Hellings, Geert ^a   Thijs, Steven ^a   Linten, Dimitri ^a   Scholz, Mirko ^b   Groeseneken, Guido ^c  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BULK FINFET; CMOS NODES; CMOS TECHNOLOGY; ESD PERFORMANCE; SIGNIFICANT DETERIORATIONS; TECHNOLOGY OPTIONS;

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUITS;

ELECTROSTATIC DEVICES;

EID: 84890539564     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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