Pushing CMOS beyond the roadmap

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 63-68

  Risch, L ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FLASH MEMORY; GATES (TRANSISTOR); MOSFET DEVICES; NANOTECHNOLOGY; QUANTUM ELECTRONICS;

ELECTROSTATIC CHANNEL CONTROL; MULTI-GATE TRANSISTORS; NANOELECTRONICS; SILICON CHANNELS;

CMOS INTEGRATED CIRCUITS;

EID: 33751441247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546585     Document Type: Conference Paper

References (14)

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2. nd edition), Boston, MA, Kluwer, 1997
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6. S.Harrison et al.,"Highly Performant Double Gate MOS-FET Realized with SON Process,"IEDM TD, 2003, p.449
7. M. Vinet et al.,"High Performance 10nm bonded planar double metal gate CMOS transistors,"IEEE-EDL, issue of May 2005
8. B.Yu et al.,"FinFET Scaling to 10nm Gate Length," IEDM Technical Digest, 2002, p.251.
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10. S.Monfray et al.,"SON technological CMOS Platform: Highly performant devices and SRAM cells,"IEDM TD, 2004, p.635
11. S-Y.Lee et al.,"A Novel Sub 50nm Multi-Bridge-Channel MOSFET(MBCFET) with Extremely High Performance,"2004 Symp. VLSI Technology, p.200
12. M.Städele et al.,"Atomistic tight-binding calculations for the transport in extremely scaled SOI devices,"IEDM TD 2003, p.229
13. J.Willer et al.,"110nm NROM Technology for Code and Data Flash Products,"2004 Symp.VLSI Technology, p.76
14. M.Specht et al.,"20nm tri-gate SONOS memory cells with multi-level operation," IEDM TD, 2004, p. 1083