High-k metal gate-bounded silicon controlled rectifier for ESD protection

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2012, Pages

  Chang, Tzu Heng ^a   Hsu, Yu Ying ^a   Tsai, Tsung Che ^a   Tseng, Jen Chou ^a   Lee, Jam Wem ^a   Song, Ming Hsiang ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CURRENTS; ESD PROTECTION; HIGH SPEED I/O; LOW LEAKAGE; METAL GATE; THIN OXIDES;

EID: 84869821738     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. I M. Mergens et al., 'Diode-triggered SCR (DTSCR) for RF-ESD protection ofBiCMOS SiGe HBTs and CMOS ultra-thin gate oxides', Proceedings IEDM, 2003.
2. Amitava Chatterjee et al., 'A low-voltage triggering SCR for on-chip ESD protection at output and input pads' Proceedings IEEE EDL, 1991.
3. S. H. Chen et al., 'Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection' Proceedings IEEE TED, 2009.
4. JEDEC standard, document named JESD22C101E.
5. S. Thijs et al., 'CDM and HBM Analysis of ESD Protected 60 GHz Power Amplifier in 45 nm LowPower Digital CMOS', Proceedings EOS/ESD Symposium 2009.
6. M.H. Song et al., 'A Contribution to the Evaluation of HMM for 10 Design' Proceedings EOS/ESD Symposium 2011, pp 4B.1-1
7. HPPI, TLP 3010C, vf-TLP/HMM system.
8. Hanwa, HED-W5100D HMM system
9. Barth, 4012, vf-TLP system.
10. M. D. Ker et al., ' Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology' Proceedings IEEE JSSC, PP 1158-1168, 2007.