Write intensity prediction for energy-efficient non-volatile caches

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2013, Pages 223-228

  Ahn, Junwhan ^a   Yoo, Sungjoo ^b   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

^b Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK PLACEMENT; CACHE BLOCKS; ENERGY EFFICIENT; HYBRID CACHES; INTENSITY PREDICTION; MEMORY ACCESS; NON-VOLATILE; NOVEL CONCEPT;

ENERGY EFFICIENCY; ENERGY UTILIZATION; LOW POWER ELECTRONICS; RANDOM ACCESS STORAGE;

FORECASTING;

EID: 84889603007     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2013.6629298     Document Type: Conference Paper

References (16)

1. G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, "A novel architecture of the 3D stacked MRAM L2 cache for CMPs," in Proc. Int. Symp. High Performance Comput. Archit., 2009, pp. 239-249.
2. X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie, "Power and performance of read-write aware hybrid caches with non-volatile memories," in Proc. Design Automat. Test Eur. Conf., 2009, pp. 737-742.
3. X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, "Hybrid cache architecture with disparate memory technologies," in Proc. Int. Symp. Comput. Archit., 2009, pp. 34-45.
4. J. Li, C. J. Xue, and Y. Xu, "STT-RAM based energy-efficiency hybrid cache for CMPs," in Proc. Int. Conf. VLSI and System-on-Chip, 2011, pp. 31-36.
5. Y.-T. Chen, J. Cong, H. Huang, C. Liu, R. Prabhakar, and G. Reinman, "Static and dynamic co-optimizations for blocks mapping in hybrid caches," in Proc. Int. Symp. Low Power Electron. Design, 2012, pp. 237-242.
6. Q. Li, M. Zhao, C. J. Xue, and Y. He, "Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache," in Proc. Int. Conf. Lang. Compil. Tools Theory Embedded Syst., 2012, pp. 109-118.
7. Y. Li, Y. Chen, and A. K. Jones, "A software approach for combating asymmetries of non-volatile memories," in Proc. Int. Symp. Low Power Electron. Design, 2012, pp. 191-196.
8. G. Tyson, M. Farrens, J. Matthews, and A. R. Pleszkun, "A modified approach to data cache management," in Proc. Int. Symp. Microarchit., 1995, pp. 93-103.
9. S. Khan, Y. Tian, and D. A. Jiménez, "Sampling dead block prediction for last-level caches," in Proc. Int. Symp. Microarchit., 2010, pp. 175-186.
10. C.-J. Wu, A. Jaleel, W. Hasenplaugh, M. Martonosi, S. C. Steely Jr., and J. Emer, "SHiP: Signature-based hit predictor for high performance caching," in Proc. Int. Symp. Microarchit., 2011, pp. 430-441.
11. Q. Li, J. Li, L. Shi, C. J. Xue, and Y. He, "MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems," in Proc. Int. Symp. Low Power Electron. Design, 2012, pp. 351-356.
12. T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An infrastructure for computer system modeling," IEEE Computer, vol. 35, pp. 59-67, Feb. 2002.
13. J. L. Henning, "SPEC CPU2000: Measuring CPU performance in the new millennium," IEEE Computer, vol. 33, pp. 28-35, Jul. 2000.
14. A. J. KleinOsowski and D. J. Lilja, "MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research," IEEE Comput. Archit. Lett., vol. 1, Jan.-Dec. 2002.
15. N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, "CACTI 6.0: A tool to model large caches," HP Laboratories, Tech. Rep. HPL-2009-85, 2009.
16. X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, "NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 31, pp. 994-1007, Jul. 2012.