메뉴 건너뛰기




Volumn 60, Issue 5, 2013, Pages 1786-1789

Modeling of parasitic fringing capacitance in multifin trigate FinFETs

Author keywords

Analytical model; FinFET; Multifin; Parasitic capacitance

Indexed keywords

CONFORMAL MAPPING TECHNIQUE; FIN NUMBERS; FINFET; FRINGING CAPACITANCE; MODEL FITTING; MULTIFIN; NONDIMENSIONALIZATION; PARASITIC CAPACITANCE;

EID: 84887054407     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2013.2252467     Document Type: Article
Times cited : (25)

References (9)
  • 1
    • 21044447633 scopus 로고    scopus 로고
    • On the feasibility of nanoscale triple-gate CMOS transistors
    • DOI 10.1109/TED.2005.848109
    • W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple gate CMOS transistors," IEEE Trans. Electron. Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005. (Pubitemid 40871151)
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.6 , pp. 1159-1164
    • Yang, J.-W.1    Fossum, J.G.2
  • 2
    • 79955543198 scopus 로고    scopus 로고
    • Parasitic capacitance: Analytical models and impact on circuit-level performance
    • May
    • L.Wei, F. Boeuf, T. Skotnicki, and H.-S. P.Wong, "Parasitic capacitance: Analytical models and impact on circuit-level performance," IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1361-1370, May 2011.
    • (2011) IEEE Trans. Electron Devices , vol.58 , Issue.5 , pp. 1361-1370
    • Wei, L.1    Boeuf, F.2    Skotnicki, T.3    Wong, H.-S.P.4
  • 3
    • 13344270339 scopus 로고    scopus 로고
    • Modeling and optimization of fringe capacitance of nanoscale DGMOS devices
    • DOI 10.1109/TED.2004.842713
    • A. Bansal, B. C. Paul, and K. Roy, "Modeling and optimization of fringe capacitance of nanoscale DGMOS devices," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 256-262, Feb. 2005. (Pubitemid 40195973)
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.2 , pp. 256-262
    • Bansal, A.1    Paul, B.C.2    Roy, K.3
  • 4
    • 34147183634 scopus 로고    scopus 로고
    • Analysis of geometry-dependent parasitics in multifin double-gate FinFETs
    • DOI 10.1109/TED.2007.891252
    • W. Wu and M. Chan, "Analysis of geometry-dependent parasitics in multifin double-gate FinFETs," IEEE Trans. Electron Devices, vol. 54, no. 4, pp. 692-698, Apr. 2002. (Pubitemid 46563361)
    • (2007) IEEE Transactions on Electron Devices , vol.54 , Issue.4 , pp. 692-698
    • Wu, W.1    Chan, M.2
  • 5
    • 84860256442 scopus 로고    scopus 로고
    • Comprehensive and accurate parasitic capacitance models for two- and three-dimensional CMOS device structures
    • May
    • J. Lacord, G. Ghibaudo, and F. Boeuf, "Comprehensive and accurate parasitic capacitance models for two- and three-dimensional CMOS device structures," IEEE Trans. Electron Devices, vol. 59, no. 5, pp. 1332-1344, May 2012.
    • (2012) IEEE Trans. Electron Devices , vol.59 , Issue.5 , pp. 1332-1344
    • Lacord, J.1    Ghibaudo, G.2    Boeuf, F.3
  • 8
    • 84887037534 scopus 로고    scopus 로고
    • Synopsys Mountain View, CA USA
    • Raphael User Guide, Synopsys, Mountain View, CA, USA, 2009.
    • (2009) Raphael User Guide


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.