A family of adders

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2001, Pages 277-284

  Knowles, S ^a  

^a Aztec Centre   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; DATA STRUCTURES; GRAPH THEORY; MATHEMATICAL OPERATORS;

PARALLEL PREFIX ADDERS;

ADDERS;

EID: 0034864101     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. A logic for high-speed addition
2. A high-speed electronic arithmetic unit for automatic computing machines
3. Conditional-sum addition logic
4. Carry-select adder
5. Parallel prefix computation
6. A parallel algorithm for the efficient solution of a general class of recurrence equations
7. On the algorithmic complexity of discrete functions
8. A regular layout for parallel adders
9. Fast area-efficient VLSI adders
10. A GaAs 32-bit adder
11. The redundant cell adder