Compressive self-powering of piezo-floating-gate mechanical impact detectors

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 60, Issue 9, 2013, Pages 2311-2320

  Sarkar, Pikul ^a   Chakrabartty, Shantanu ^a  

^a Michigan State University   (United States)

Author keywords

Compressive powering; floating gate transistor; mechanical impact detection; piezoelectricity; self powered sensors; strain; structural health monitoring

Indexed keywords

CRYSTALLOGRAPHY; DYNAMIC LOADS; PIEZOELECTRICITY; STRAIN;

COMPRESSIVE POWERING; FLOATING GATE TRANSISTORS; MECHANICAL IMPACTS; MECHANICAL STRAIN; NONLINEAR IMPEDANCE; PROGRAMMING TECHNIQUE; SELF-POWERED; STANDARD CMOS PROCESS;

STRUCTURAL HEALTH MONITORING;

EID: 84883465945     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2013.2245472     Document Type: Article

References (20)

1. C. Huang and S. Chakrabartty, "An asynchronous analog self-powered CMOS sensor-data-logger with a 13.56 MHz RF programming inter face, " IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 476-489, Feb. 2012.
2. R. Amirtharajah and A. P. Chandrakasan, "Self-powered signal processing using vibration-based power generation, " IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 687-695, May 1998. (Pubitemid 128573473)
3. Y. K. Ramadass and A. P. Chandrakasan, "A battery-less thermoelectric energy harvesting interface circuit with 35 mV startup voltage, " IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 333-341, Jan. 2011.
4. Y. L. Lee, J. Pan, R. Hathaway, and M. Barkey, Fatigue Testing and Analysis: Theory and Practice, 2004.
5. S. Suresh, Fatigue of Materials, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 1998, 10: 0521578477.
6. D. S. Peerce and V. S. Berg, "Bullet impact on steel and kevlar/steel armor-computer modelling and experimental data, " in Proc. ASME Conf. Proc., 2004, vol. 207.
7. K. Fujii, E. Yasuda, and Y. Tanabe, "Dynamic mechanical properties of polycrystalline graphites and a 2D-C/C composite by plate impact, " Int. J. Impact Eng., vol. 25, no. 5, pp. 473-491, May 2001. (Pubitemid 32272876)
8. M. Grujicic, T. He, H. Marvi, B. A. Cheeseman, and C. F. Yen, "A comparative investigation of the use of laminate-level meso-scale and fracture-mechanics-enriched meso-scale composite-material models in ballistic-resistance analyses, " J. Mater. Sci., vol. 45, no. 12, pp. 3136-3150.
9. C. Huang, N. Lajnef, and S. Chakrabartty, "Calibration and characterization of self-powered floating-gate usage monitor with single electron per second operational limit, " IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 57, no. 3, pp. 556-567, Mar. 2010.
10. C. Huang, P. Sarkar, and S. Chakrabartty, "Rail-to-rail, linear hot-electron injection programming of floating-gate voltage bias generators at 13-bit resolution, " IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2685-2962, Nov. 2011.
11. P. Sarkar, C. Huang, and S. Chakrabartty, "An ultra-linear Piezo-floating-gate strain-gauge for self-powered measurement of quasistatic-strain, " IEEE Trans. Biomed. Circuits Syst., to be published.
12. N. G. Elvin and A. A. Elvin, "A general equivalent circuit model for piezoelectric generators, " J. Intell. Syst. Structures, vol. 20, no. 1, pp. 3-9, Jan. 2009.
13. S. Chakrabartty and N. Lajnef, "Infrasonic power-harvesting and nanowatt self-powered sensors, " in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2009, pp. 157-160.
14. N. Yan and H. Min, "A high efficiency all-PMOS charge pump for low-voltage operations, " in Proc. IEEE Asian Solid-State Circuits Conf., Hsinchu, Taiwan, Nov. 2005, p. 361364.
15. R. Pelliconi and D. Iezzi et al., "Power efficient charge pump in deep submicron standard CMOS technology, " IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1068-1071, Jun. 2003.
16. P. Hasler, "Foundations of Learning in Analog VLSI, " Ph.D. dissertation, Dept. Comput. Neural Syst., California Inst. Technol., Pasadena, CA, USA, 1997.
17. Y. L. Wong, M. H. Cohen, and P. A. Abshire, "A floating-gate comparator with automatic offset adaptation for 10-bit data conversion, " IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 7, pp. 1316-1326, Jul. 2005. (Pubitemid 41081624)
18. V. Srinivasan, G. J. Serrano, J. Gray, and P. Hasler, "A precision CMOS amplifier using floating-gate transistors for offset cancellation, " IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 280-291, Feb. 2007. (Pubitemid 46374513)
19. R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch, and S. P. Deweerth, "A CMOS programmable analog memory-cell array using floating-gate circuits, " IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., vol. 48, no. 1, p. 411, Jan. 2001.
20. K. Rahimi, C. Diorio, C. Hernandez, and M. D. Brockhausen, "A simulation model for floating-gate MOS synapse transistors, " in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Phoenix, AZ, May 2002, pp. 532-535.