A high efficiency ALL-PMOS charge pump for low-voltage operations

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 361-364

  Yan, Na ^a   Min, Hao ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

Boosted transistor; Charge pump; Low voltage; Number of stage; Power efficiency; Standard CMOS process

Indexed keywords

BANDWIDTH; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; STANDARDS; SUBSTRATES; TRANSISTORS;

BOOSTED TRANSISTORS; CHARGE PUMP; LOW VOLTAGE; OUTPUT VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 34250719161     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251740     Document Type: Conference Paper

References (5)

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2. Umezawa, et al, "A 5V-only operation 0.6-um flash EEPROM with row decoder scheme in triple-well structure", IEEE. JSSC, vol. 27, no. 11, pp. 1540-1646, Nov. 1992.
3. R.Pelliconi, D.Iezzi et al, "Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology," IEEE JSSC, vol.38, No.6, June 2003.
4. Gaetano Palumbo, Domenico Pappalardo, and Maurizio Gaibotti, "Charge-Pump Circuits: Power-Consumption Optimization," IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol.49, No.11,Nov 2002.
5. Jongshin Shin, In-Yong Chung, Young June Park, and Hong Shick Min, "A New Charge Pump Without Degradation in Threshold Voltage Due to Body Effect," IEEE JSSC,vol.35,No.8, May 2000.