Parallel Viterbi algorithm for a VLIW DSP

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 6, Issue , 2000, Pages 3390-3393

  Khan, Shoab Ahmad ^a   Saqib, Malik M ^b   Ahmed, Sherjil ^b  

^a NATIONAL UNIVERSITY OF SCIENCES AND TECHNOLOGY   (Pakistan)

^b Communications Enabling Technologies ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; DIGITAL SIGNAL PROCESSING; VERY LONG INSTRUCTION WORD ARCHITECTURE; VITERBI ALGORITHM; COMMUNICATION SATELLITES; DEMODULATORS; IMAGE CODING; MICROPROCESSOR CHIPS; MODEMS;

COMPUTATIONALLY INTENSIVE ALGORITHMS; CONVOLUTIONAL DECODERS; HIGH DATA RATE; HIGH DATA RATE SATELLITE; RECEIVER ALGORITHMS; RUNNING TESTS; SATELLITE RECEIVERS; VITERBI DECODER;

SIGNAL PROCESSING; PARALLEL ALGORITHMS;

PARALLEL VITERBI ALGORITHM; VERY LONG INSTRUCTION WORD DIGITAL SIGNAL PROCESSORS;

EID: 0033724504     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2000.860128     Document Type: Conference Paper

References (8)

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