Low-temperature monolithic three-layer 3-D process for FPGA

IEEE Electron Device Letters

Volumn 34, Issue 8, 2013, Pages 1044-1046

  Zhang, Zhiping ^a   Chen, Chien Yu ^a   Crnogorac, Filip ^a   Chen, Shu Lu ^a   Griffin, Peter B ^a   Pease, R Fabian ^a   Plummer, James D ^a   Wong, S Simon ^a  

^a Stanford University   (United States)

Author keywords

Field programmable gate array (FPGA); fusion bonding; GePMOS; monolithic 3 D IC; resistive random access memory (RRAM)

Indexed keywords

3-D INTEGRATED CIRCUIT; FUSION BONDING; GEPMOS; GERMANIUMS (GE); HYDROGEN IONS; LOW TEMPERATURES; RESISTIVE RANDOM ACCESS MEMORY (RRAM); SWITCHED CURRENTS;

GERMANIUM; SILICON WAFERS; TEMPERATURE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84881026678     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2266111     Document Type: Article

References (12)

1. P. Garou, C. Bower, and P. Ramm, Handbook of 3D Integration, vols. 1-2. New York, NY, USA: Wiley, 2008.
2. C. S. Tan, K. N. Chen, and S. J. Koester, 3D Integration for VLSI Systems. Boca Raton, FL, USA: Pan Stanford, 2012.
3. B. Rajendran, "Sequential 3D IC fabrication: Challenges and prospects," in Proc. VLSI Multi Level Interconnect Conf., 2006, pp. 57-64.
4. C. Liu and S. K. Lim, "A design tradeoff study with monolithic 3D integration," in Proc. 13th Int. Symp. Qual. Electron. Design, 2012, pp. 529-536.
5. W. Kim, S. I. Park, Z. Zhang, et al., "Forming-free nitrogen-doped AlOX RRAM with sub-?A programming current," in Proc. Symp. VLSI Technol., Jun. 2011, pp. 22-23.
6. Y. Yang-Liauw, Z. Zhang, W. Kim, et al., "Nonvolatile 3D-FPGA with monolithically stacked RRAM based configuration memory," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 406-407.
7. M. Lin, A. El Gamal, Y.-C. Liu, et al., "Performance benefit of monolithically stacked 3-D FPGA," in Proc. IEEE Int. Symp. Field-Program. Gate Arrays, Feb. 2006, pp. 113-122. (Pubitemid 44032244)
8. J. S. Park, M. Curtin, J. M. Hydrick, et al., "Low-defect-density Ge epitaxy on Si(001) using aspect ratio trapping and epitaxial lateral overgrowth," Electrochem. Solid-State Lett., vol. 12, no. 4, pp. H142-H144, 2009.
9. J. Feng, Y. Liu, P. Griffin, et al., "Integration of germanium-on-insulator and silicon MOSFETs on a silicon substrate," IEEE Electron. Dev. Lett., vol. 27, no. 11, pp. 911-913, Nov. 2006. (Pubitemid 44660650)
10. C. S. Tan and R. Reif, "Silicon multilayer stacking based on copper wafer bonding," Electrochem. Solid-State Lett., vol. 8, no. 6, pp. G147-G149, 2005. (Pubitemid 40860713)
11. F. Crnogorac, S. Wong, and R. F. W. Pease, "Semiconductor crystal islands for three-dimensional integration," J. Vac. Sci. Technol. B, vol. 28, no. 6, pp. 53-58, Nov.-Dec. 2010.
12. J. Feng, G. Thareja, M. Kobayashi, et al., "High-performance gateall-around GeOI p-MOSFETs fabricated by rapid melt growth using plasma nitridation and ALD Al2O3 gate dielectric and self-aligned NiGe contacts," IEEE Electron. Dev. Lett., vol. 29, no. 7, pp. 805-807, Jul. 2008.