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Volumn , Issue , 2012, Pages 529-536

A design tradeoff study with monolithic 3D integration

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3-D INTEGRATION; 3D DESIGN; 3D TECHNOLOGY; DESIGN CHALLENGES; DESIGN STYLES; DESIGN TRADEOFF; GLOBAL VARIATIONS; MONOLITHIC INTEGRATION; PARASITICS; SIGNAL INTEGRITY; TECHNOLOGY IMPROVEMENT; WIRE LENGTH;

EID: 84863703091     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2012.6187545     Document Type: Conference Paper
Times cited : (82)

References (11)
  • 3
    • 76349107581 scopus 로고    scopus 로고
    • A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated with Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application
    • S.-M. Jung et al., "A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated With Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application," in IEEE Trans. on Electron Devices, 2010.
    • (2010) IEEE Trans. on Electron Devices
    • Jung, S.-M.1
  • 4
    • 84863670673 scopus 로고    scopus 로고
    • Sequential 3D IC Fabrication: Challenges and Prospects
    • B. Rajendran, "Sequential 3D IC Fabrication: Challenges and Prospects,"in IEEE Trans. on Electron Devices, 2010.
    • (2010) IEEE Trans. on Electron Devices
    • Rajendran, B.1
  • 6
    • 33644640188 scopus 로고    scopus 로고
    • Stable SRAM Cell Design for the 32nm Node and Beyond
    • L. Chang et al., "Stable SRAM Cell Design for the 32nm Node and Beyond," in Symposium on VLSI Technology, 2005.
    • Symposium on VLSI Technology, 2005
    • Chang, L.1
  • 7
  • 10
    • 78650861793 scopus 로고    scopus 로고
    • Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
    • Jan.
    • G. V. der Plas et al., "Design Issues and Considerations for Low-Cost 3-D TSV IC Technology," in IEEE Journal of Solid-State Circuits, Jan. 2011, pp. 293-307.
    • (2011) IEEE Journal of Solid-State Circuits , pp. 293-307
    • Der Plas, G.V.1
  • 11
    • 50249149576 scopus 로고    scopus 로고
    • A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
    • S.-Y. Wu et al., "A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM," in Proc. IEEE Int. Electron Devices Meeting, 2007.
    • Proc. IEEE Int. Electron Devices Meeting, 2007
    • Wu, S.-Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.