Low-on-resistance strain-controlled LDMOS transistors for 0.25-μm power ICs

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn , Issue , 2011, Pages 168-171

  Miyamoto, Masafumi ^a   Sugii, Nobuyuki ^a   Kumagai, Yukihiro ^a   Kimura, Yoshinobu ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGHER EFFICIENCY; LDMOS TRANSISTORS; MECHANICAL STRESS; MECHANICAL STRESS DISTRIBUTIONS; SOURCE RESISTANCE; STRAIN-CONTROLLED; SURFACE SOURCES; UV-RAMAN SPECTROSCOPY;

ANALOG CIRCUITS; MOS DEVICES; SEMICONDUCTOR DOPING; STRESS CONCENTRATION; TENSILE STRESS; TRANSISTORS;

SURFACE RESISTANCE;

EID: 84880723880     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPSD.2011.5890817     Document Type: Conference Paper

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