Power gating applied to MP-SoCs for standby-mode power management

Proceedings - Design Automation Conference

Volumn , Issue , 2013, Pages

  Flynn, David ^a  

^a ARM LTD   (United Kingdom)

Author keywords

Central processor unit (CPU); Dynamic voltage and frequency scaling (DVFS); Electronic design automation (EDA); Energyefficiency; Implementation IP (IIP); Intellectual property (IP); Ipdeployment; Logical IP (LIP); Low power; Multi threshold cmos (MTCMOS); Multi voltage (mv); Physical IP (PIP); Power intent; Power gating (PG); Standard cell; State retention (SR); System on chip (SoC)

Indexed keywords

CENTRAL PROCESSOR UNITS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ELECTRONIC DESIGN AUTOMATION; IMPLEMENTATION IP (IIP); IPDEPLOYMENT; LOGICAL IP (LIP); LOW POWER; MULTI-THRESHOLD CMOS; MULTI-VOLTAGE; PHYSICAL IP (PIP); POWER INTENT; POWER-GATING; STANDARD-CELL; STATE-RETENTION; SYSTEM-ON-CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ENERGY EFFICIENCY; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

MULTIPROCESSING SYSTEMS;

EID: 84879877649     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488930     Document Type: Conference Paper

References (12)

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