An ARM perspective on addressing low-power energy-efficient SoC designs

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 73-77

  Flynn, David ^a  

^a ARM LTD   (United Kingdom)

Author keywords

automatic test pattern generation (atpg); central processor unit (cpu); dynamic voltage and frequency scaling (dvfs); eco system; electronic design automation (eda); energy efficiency; implementation ip (iip); intellectual property (ip); ip deployment; logical ip (lip); low power; multi threshold cmos (mtcmos); multi voltage (mv); physical ip (pip); power intent; power gating (pg); standard cell; state retention (sr); system on chip (soc)

Indexed keywords

CENTRAL PROCESSOR UNITS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ELECTRONIC DESIGN AUTOMATION; IMPLEMENTATION IP (IIP); IP-DEPLOYMENT; LOGICAL IP (LIP); LOW POWER; MULTI-THRESHOLD CMOS; MULTI-VOLTAGE; PHYSICAL IP (PIP); POWER INTENT; POWER-GATING; STANDARD-CELL; STATE-RETENTION; SYSTEM-ON-CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TEST PATTERN GENERATION; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LOW POWER ELECTRONICS; PROGRAMMABLE LOGIC CONTROLLERS;

ENERGY EFFICIENCY;

EID: 84865566728     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333680     Document Type: Conference Paper

References (11)

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