Power challenges may end the multicore era

Communications of the ACM

Volumn 56, Issue 2, 2013, Pages 93-102

  Esmaeilzadeh, Hadi ^a   Blem, Emily ^b   Amant, Renée St ^c   Sankaralingam, Karthikeyan ^b   Burger, Doug ^d  

^a UNIVERSITY OF WASHINGTON   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^d MICROSOFT RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MODELS; DARK SILICONS; ECONOMIC VIABILITY; ENERGY EFFICIENCY IMPROVEMENTS; FULL-SPEED; IN-PROCESS TECHNOLOGY; MICRO ARCHITECTURES; MICROPROCESSOR INDUSTRY; MOORE'S LAW; MULTI CORE; PARALLEL WORKLOADS; PERFORMANCE GAIN; PERFORMANCE IMPROVEMENTS; POWER CONSTRAINTS; PROCESS GENERATION; PROCESSOR CORES; RESEARCH COMMUNITIES; SILICON SCALING; TOTAL PERFORMANCE; TRANSISTOR COUNT;

COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; SILICON;

PARALLEL PROCESSING SYSTEMS;

EID: 84873690610     PISSN: 00010782     EISSN: 15577317     Source Type: Journal    
DOI: 10.1145/2408776.2408797     Document Type: Review

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