15nm HP patterning with EUV and SADP: Key contributors for improvement of LWR, LER and CDU

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 8685, Issue , 2013, Pages

  Xu, K ^a   Souriau, L ^a   Hellin, D ^b   Versluijs, J ^a   Wong, P ^a   Vangoidsenhoven, D ^a   Vandenbroeck, N ^a   Dekkers, H ^a   Shi, X P ^a   Albert, J ^a   Tan, C L ^a   Vertommen, J ^b   Coenegrachts, B ^b   Orain, I ^c   Kimura, Y ^c   Wiaux, V ^a   Boullart, W ^a  

^a IMEC   (Belgium)

^b LAM RESEARCH CORPORATION   (Belgium)

^c LAM RESEARCH CORPORATION   (United States)

Author keywords

15nm HP; CDU; EUVL; LER; LWR; SADP

Indexed keywords

15NM HP; CDU; LER; LWR; SADP;

EXTREME ULTRAVIOLET LITHOGRAPHY; PHOTORESISTS;

MECHANICAL PROPERTIES;

EID: 84878453126     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.2011586     Document Type: Conference Paper

References (10)

1. ITRS 2012, http://www.itrs.net/Links/2012ITRS/Home2012.htm.
2. Y. Chen, Technological merits, process complexity, and cost analysis of self-aligned multiple patterning, Proc. SPIE 8326, Optical Microlithography XXV, 832620; doi:10.1117/12.916490., 2012.
3. C. Bencher, Self-assembly patterning for sub-15nm half-pitch: a transition from lab to fab, SPIE Advanced Lithography. 0001;79700F-79700F-9. doi:10.1117/12.881293..
4. P. Rincon Delgadillo, All track directed self-assembly of block copolymers: process flow and origin of defects, SPIE Advanced Lithography. 0001:83230D-83230D-9. doi:10.1117/12.916410..
5. Issues of EUV lithography, EETAsia. http://www.eetasia.com/ART- 8800656186-480200-NT-a81058ff.HTM.
6. J. Finders, Double patterning for 32nm and below: an update, Proceedings of SPIE, vol. 6924.
7. E. Kunnen, Dry etch challenges in a 20 nm half-pitch single damascene spacer-defined patterning scheme, PESM 3rd international workshop, 2010.
8. Y. Ban, Electrical impact of line-edge roughness on sub-45-nm node standard cells, Journal of Micro/Nanolithography, MEMS, and MOEMS 9(04), 041206.
9. P. Poliakov, Trades-off between line edge roughness and ECCs requirements for NAND Flash memories, Journal of Microelectronics Reliability, vol. 52, pp. 525-529, 2012.
10. P. Poliakov, Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness, Journal of Microelectronics Reliability, vol. 51, pp. 919-924, 2011.