Stability and low-frequency noise in InAs NW parallel-array thin-film transistors

IEEE Electron Device Letters

Volumn 34, Issue 6, 2013, Pages 765-767

  Wahl, Richard E ^a   Wang, Fengyun ^b   Chung, Hugh E ^a   Kunnen, George R ^a   Yip, Senpo ^b   Lee, Edward H ^a   Pun, Edwin Y B ^b   Raupp, Gregory B ^b   Allee, David R ^a   Ho, Johnny C ^b  

^a Arizona State University   (United States)

^b CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

InAs; low frequency noise; nanowire (NW) parallel arrays; stability; thin film transistors (TFTs)

Indexed keywords

DC CHARACTERISTICS; DEVICE DESIGN; INAS; LOW-FREQUENCY NOISE; NUMBER FLUCTUATIONS; PARALLEL ARRAYS; THIN-FILM TRANSISTOR (TFTS); THRESHOLD VOLTAGE SHIFTS;

CONVERGENCE OF NUMERICAL METHODS; NANOWIRES; THIN FILM TRANSISTORS;

INDIUM ARSENIDE;

EID: 84878274276     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2250896     Document Type: Article

References (12)

1. A. C. Ford, J. C. Ho, Z. Fan, O. Ergen, V. Altoe, H. Razavi, and A. Javey, "Synthesis, contact printing, and device characterization of Ni-catalyzed, crystalline InAs NWs," Nano Res., vol. 1, no. 1, pp. 32-39, Jul. 2008.
2. T. Bryllert, L. E. Wernersson, L. E. Froberg, and L. Samuelson, "Vertical high-mobility wrap-gated InAs nanowire transistor," IEEE Electron Device Lett., vol. 27, no. 5, pp. 323-325, May 2006.
3. K. M. Persson, E. Lind, A. W. Dey, C. Thelander, H. Sjoland, and L. E. Wernersson, "Low-frequency noise in vertical InAs nanowire FETs," IEEE Electron Device Lett., vol. 31, no. 5, pp. 428-430, May 2010.
4. M. R. Sakr and X. P. A. Gao, "Temperature dependence of the low frequency noise in indium arsenide nanowire transistors," Appl. Phys. Lett., vol. 93, no. 20, pp. 203503-1-203503-3, Nov. 2008.
5. X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles, and J. L. Goldman, "High-performance thin-film transistors using semiconductor nanowires and nanoribbons," Nature, vol. 425, no. 6955, pp. 274-278, Sep. 2003. (Pubitemid 37158399)
6. Z. Fan, J. C. Ho, Z. A. Jacobson, R. Yerushalmi, R. L. Alley, H. Razavi, and A. Javey, "Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing," Nano Lett., vol. 8, no. 1, pp. 20-25, Jan. 2008. (Pubitemid 351177769)
7. K. Kaftanoglu, S. M. Venugopal, M. Marrs, A. Dey, E. J. Bawolek, D. R. Allee, and D. Loy, "Stability of IZO and a-Si:H TFTs processed at low temperature (200 °C)," J. Display Technol., vol. 7, no. 6, pp. 339-343, Jun. 2011.
8. D. R. Khanal and J. Wu, "Gate coupling and charge distribution in nanowire field effect transistors," Nano Lett., vol. 7, no. 9, pp. 2778-2783, Aug. 2007. (Pubitemid 47522438)
9. J. Zhuge, R. Wang, R. Huang, Y. Tian, L. Zhang, D. W. Kim, D. Park, and Y. Wang, "Investigation of low-frequency noise in silicon nanowire MOSFETs," IEEE Electron Device Lett., vol. 30, no. 1, pp. 57-60, Jan. 2009.
10. M. von Haartman and M. Östling, Low-Frequency Noise in Advanced MOS Devices. New York, USA: Springer-Verlag, 2007.
11. R. Jayaraman and C. G. Sodini, "A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon," IEEE Trans. Electron Dev., vol. 36, no. 9, pp. 1773-1782, Sep. 1989. (Pubitemid 20617806)
12. Y. F. Lim, Y. Z. Xiong, N. Singh, R. Yang, Y. Jiang, D. S. H. Chan, W. Y. Loh, L. K. Bera, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Random telegraph signal noise in gate-all-around Si-FinFET with ultranarrow body," IEEE Electron Device Lett., vol. 27, no. 9, pp. 765-768, Sep. 2006. (Pubitemid 44355900)