High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2013, Pages 19-24

  Syu, Shun Ming ^a   Shao, Yu Hui ^a   Lin, Ing Chao ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

cache partitioning; hybrid cache; stt ram; wear leveling

Indexed keywords

CACHE PARTITIONING; CHIP MULTI-PROCESSORS; HYBRID CACHES; NON-VOLATILE MEMORY; PHASE CHANGE RAMS; SPIN TRANSFER TORQUE; STT RAMS; WEAR LEVELING;

DATA STORAGE EQUIPMENT;

EID: 84878206095     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2483028.2483052     Document Type: Conference Paper

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