Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2013, Pages 338-343

  Kuo, Hsien Kai ^a   Yen, Ta Kan ^a   Lai, Bo Cheng Charles ^a   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MISS REDUCTION; COMPLEX APPLICATIONS; CONCURRENT THREADS; IRREGULAR APPLICATIONS; MEMORY BOTTLENECK; PERFORMANCE DEGRADATION; SCHEDULING SCHEMES; THREAD SCHEDULING;

COMPUTER AIDED DESIGN; PROGRAM PROCESSORS;

SCHEDULING;

EID: 84877739484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2013.6509618     Document Type: Conference Paper

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