Thread affinity mapping for irregular data access on shared cache GPGPU

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2012, Pages 659-664

  Kuo, Hsien Kai ^a   Chen, Kuan Ting ^a   Lai, Bo Cheng Charles ^a   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT THREADS; DATA SHARING; IRREGULAR DATA; MANY-CORE; MAPPING METHODOLOGY; MEMORY ACCESS; MEMORY BOTTLENECK; ON CHIPS; PERFORMANCE BENEFITS; RUNTIMES; SHARED CACHE; TEST CASE;

COMPUTER AIDED DESIGN; FLOCCULATION; PROGRAM PROCESSORS;

CACHE MEMORY;

EID: 84860003663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2012.6165038     Document Type: Conference Paper

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