A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 280-281

  Liou, Chang Yuan ^a   Hsieh, Chih Cheng ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BIOMEDICAL DEVICES; LOW-POWER OPERATION; RESEARCH INTERESTS; SUCCESSIVE APPROXIMATION REGISTER; SWITCHING ENERGY; UNIT CAPACITANCE; VARIABLE SAMPLING RATES; VOLTAGE REFERENCE;

CALIBRATION; ENERGY EFFICIENCY; WIRELESS SENSOR NETWORKS;

CAPACITORS;

EID: 84876515690     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487735     Document Type: Conference Paper

References (6)

1. H.-Y. Tai, et al., "A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS," IEEE Symp. VLSI Circuits, pp. 92-93, June 2012
2. A. Shikata, et al., "A 0.5 V 1.1MS/sec 6.3fJ/Conversion-Step SAR-ADC with Tri-Level Comparator in 40 nm CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1022-1030, Apr. 2012
3. P. Harpe, et al., "A 7-To-10b 0-To-4MS/s Flexible SAR ADC with 6.5-To-16fJ/conversion-step," ISSCC Dig. Tech. Papers, pp. 472-474, Feb. 2012
4. M. van Elzakker, et al., "A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1MS/s," IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010
5. V. Hariprasath, et al., "Merged Capacitor Switching Based SAR ADC with Highest Switching Energy-Efficiency," IET Electronics Letters, Apr. 2010
6. H.-Y. Huang, et al., "A 9.2b 47fJ/Conversion-step Asynchronous SAR ADC with Input Range Prediction DAC Switching," IEEE ISCAS, pp. 2353-2356, May 2012