A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 472-473

  Harpe, Pieter ^a,b   Zhang, Yan ^a   Dolmans, Guido ^a   Philips, Kathleen ^a   De Groot, Harmke ^a  

^a HOLST CENTRE   (Netherlands)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

POWER EFFICIENCY; POWER EFFICIENT; REDUCING COSTS; SAMPLE RATE; SAR ADC; SENSOR APPLICATIONS; ULTRA-LOW POWER; WIRELESS SENSOR NODE;

EFFICIENCY; ELECTRIC NETWORK SYNTHESIS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 84860651934     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177096     Document Type: Conference Paper

References (5)

1. M. van Elzakker, et al., "A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1MS/s," IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
2. A. Shikata, et al., "A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS," IEEE Symp. VLSI Circuits, pp. 262-263, June 2011.
3. P. Harpe, et al., "A 26μW 8bit 10MS/s Asynchronous SAR ADC for Low Energy Radios," IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, July 2011.
4. M. Yip and A. P. Chandrakasan, "A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC," ISSCC Dig. Tech. Papers, pp. 190-191, Feb. 2011.
5. V. Giannini, et al., "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008.