A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 92-93

  Tai, Hung Yen ^a   Chen, Hung Wei ^a   Chen, Hsin Shu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

low power; Low voltage; SAR ADC

Indexed keywords

90NM CMOS; CAPACITOR ARRAYS; CHARGE PUMP; COMMON MODE; CONVERSION TIME; DIFFERENTIAL CONTROL; ENERGY EFFICIENT; LEAKAGE REDUCTION; LEVEL SHIFT; LOW POWER; LOW VOLTAGES; LOW-VOLTAGE; NYQUIST RATE; SAR ADC;

VLSI CIRCUITS;

EID: 84866618101     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243805     Document Type: Conference Paper

References (3)

1. M. V. Elzakker, et al., "A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC," IEEE ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2008.
2. F. Kuttner, "A 1.2V 10b 20MSamples/s non-binary successive approximation ADC in 0.13μm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002.
3. C. C. Liu, et al, "A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure," IEEE Journal of Solid-State Circuits, vol. 45, no.4, pp. 731-740, April 2010.