Integration of solid-state nanopores in a 0.5 μm CMOS foundry process

Nanotechnology

Volumn 24, Issue 15, 2013, Pages

  Uddin, A ^a   Yemenicioglu, S ^a   Chen, C H ^a   Corigliano, E ^a   Milaninia, K ^a   Theogarajan, L ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; EXPERIMENTAL VALUES; FABRICATION PROCESS; NANOPORE MEMBRANES; POLYSILICON CAPACITORS; SOLID-STATE NANOPORE; THEORETICAL MODELS; TRANSMISSION ELECTRON MICROSCOPE;

ALUMINUM COATINGS; ATOMIC LAYER DEPOSITION; CMOS INTEGRATED CIRCUITS; DEPOSITION; ELECTRODES; ELECTRON BEAM LITHOGRAPHY; FABRICATION; MEMBRANE TECHNOLOGY; POLYSILICON; SEMICONDUCTOR DEVICES; SILICON NITRIDE; TRANSMISSION ELECTRON MICROSCOPY; VOLTAGE REGULATORS;

NANOPORES;

DNA; SILICON DIOXIDE;

ARTICLE; CHEMISTRY; ELECTRIC CONDUCTIVITY; EQUIPMENT; ISOLATION AND PURIFICATION; METHODOLOGY; NANOPORE; NANOTECHNOLOGY; PARTICLE SIZE; REPRODUCIBILITY; SEMICONDUCTOR; TRANSMISSION ELECTRON MICROSCOPY; ULTRASTRUCTURE;

DNA; ELECTRIC CONDUCTIVITY; MICROSCOPY, ELECTRON, TRANSMISSION; NANOPORES; NANOTECHNOLOGY; PARTICLE SIZE; REPRODUCIBILITY OF RESULTS; SEMICONDUCTORS; SILICON DIOXIDE;

EID: 84875664029     PISSN: 09574484     EISSN: 13616528     Source Type: Journal    
DOI: 10.1088/0957-4484/24/15/155501     Document Type: Article

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