Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 741-746

  Hwang, Chanseok ^a   Kang, Changwoo ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN METHODOLOGY; GROUND NETWORKS; LOGIC RESTRUCTURING; MTCMOS CIRCUITS; MULTI-THRESHOLD CMOS; PARASITIC RESISTANCES; SLEEP TRANSISTORS; SUB-THRESHOLD LEAKAGE CURRENTS;

CMOS INTEGRATED CIRCUITS; DESIGN; LEAKAGE CURRENTS; LOGIC CIRCUITS; LOGIC DEVICES; TRANSISTORS;

GATES (TRANSISTOR);

EID: 84874651323     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.70     Document Type: Conference Paper

References (10)

1. C. Long and L. He, "Distributed Sleep Transistor Network for Power reduction", In Proceedings of the ACM/IEEE DAC, 181-186, 2003.
2. P. Babighian, L. Benini, A. Macii and E. Macii, "Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion", In Proceedings of the ISLPED, 138-143, 2004.
3. S. Mutoh et al. "1-V Power Supply High Speed Digital Circuit Technology with Multithreshold-Voltages CMOS", In IEEE JSSC, vol. 30, no.8, Aug. 1995.
4. J. Kao, A. Chandrakasan and D. Antoniadis, "Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology", In Proceedings of the ACM/IEEE DAC, 409-414, 1997.
5. J. Kao, S. Narenda and A. Chandrakasan, "MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns", In Proceedings of the ACM/IEEE DAC, 495-500, 1998.
6. M. Anis, S. Areibi, M. Mahmoud and M. Elmasry, "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique", In Proceedings of the ACM/IEEE DAC, 480-485, 2002.
7. A. Abdollahi, F. Fallah and M. Pedram, "An Effective Power Mode Transition Technique in MTCMOS Circuits", In Proceedings of the ACM/IEEE DAC, 37-42, 2005.
8. V. Khandelwal and A. Srivastava, "Leakage Control through Fine-Grained Placement and Sizing of Sleep Transistors", In Proceedings of the ACM/IEEE ICCAD, 533-536, 2004.
9. O. Coudert, "Gate Sizing for Constrained Delay/Power/Area Optimization", In IEEE Trans. on VLSI, 465-472, Dec. 2005.
10. Sproull, R. F., and I. E. Sutherland, "Logical Effort: Designing for Speed on the Back of an Envelop", IEEE Advanced Research in VLSI, C. Sequin (editor), MIT Press, 1991.