System-level performance optimization and benchmarking for on-chip graphene interconnects

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012

Volumn , Issue , 2012, Pages 33-36

  Pan, Chenyun ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Graphene; interconnect; system level optimization

Indexed keywords

COPPER WIRES; DIE SIZE; EXECUTION TIME; INTERCONNECT; MULTI-CORE PROCESSOR; MULTICORE CHIPS; ON CHIPS; OUTPUT RESISTANCE; POWER DENSITIES; SYSTEM LEVEL OPTIMIZATION; SYSTEM-LEVEL PERFORMANCE; WIRE LENGTH;

ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; OPTIMIZATION; WIRE;

GRAPHENE;

EID: 84874469288     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2012.6457837     Document Type: Conference Paper

References (10)

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