System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model

ICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology

Volumn , Issue , 2012, Pages

  Pan, Chenyun ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

empirical CPI model; graphene pn junction; system level optimization; throughput

Indexed keywords

CMOS TECHNOLOGY; CYCLES PER INSTRUCTIONS; DETAILED DESIGN; DEVICE TECHNOLOGIES; DIE SIZE; EMERGING TECHNOLOGIES; LOGIC SYSTEMS; MAXIMUM THROUGH-PUT; NOVEL DEVICES; P-N JUNCTION; PN-JUNCTION DEVICES; POWER DENSITIES; SYSTEM LEVEL OPTIMIZATION; SYSTEM-LEVEL PERFORMANCE; TECHNOLOGY DEVELOPMENT; TECHNOLOGY NODES;

CMOS INTEGRATED CIRCUITS; GRAPHENE; TECHNOLOGY; THROUGHPUT;

OPTIMIZATION;

EID: 84864688851     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2012.6232850     Document Type: Conference Paper

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